Texas Instruments TMS320TCI648x manual Haddrcapt

SRIO Registers

G

GBL_EN 116

GBL_EN_STAT 117 global enable bit 116 global enable status bit 118

global enabling/disabling of all logical blocks 71

H

H_ADDR_CAPT 214
head descriptor pointer field for RX queue n		166
head descriptor pointer field for TX queue n		164
header fields
doorbell operation 64
message request packet 44
hexadecimal notational convention	14
HOP_COUNT field of LSUn_REG5	160
host base device ID lock CSR 194
host device mode field 199

I

ID_CAPT 216

ID_SIZE field of LSUn_REG4 159

idle error checking disable field for ports 231 ILL_TRANS_EN field of SPn_CTL_INDEP 236 ILL_TRANS_ERR field of SPn_CTL_INDEP 236 illegal transaction at LSU, TXU, MAU, or RXU

reporting enable field 212 status field 210

illegal transfer error at port n reporting enable field 237 status field 237

INBOUND_ACKID field of SPn_ACKID_STAT 202 INFO_TYPE field of SPn_ERR_ATTR_CAPT_DBG0

223
initialization example for message passing				61
initialization example for the SRIO peripheral 77
INITIALIZED_PORT_WIDTH field of SPn_CTL					206
initialized status bit for ports	205
initialized width field for port n	206
in-order reception of message packets		49
in-order requirement bits for RX queues			173
INPUT_ERROR_ENC field of SPn_ERR_STAT					203
INPUT_ERROR_STP field of SPn_ERR_STAT					203
INPUT_PORT_ENABLE field of SPnCTL			206
INPUT_RETRY_STP field of SPn_ERR_STAT					203
input enable field for port n 207
input error-stopped status bit for ports		204
input retry-stopped status bit for ports		204
input termination field for SERDES receiver				126
input transmission error status bit for ports				204
INTDSTn_DECODE 150
INTDSTn_RATE_CNTL 154
interconnect architecture for RapidIO		18
interfacing two 1x or 4x devices 18
INTERRUPT_REQ field of LSUn_REG4			159
interrupt approach to messaging protocol			86

246Index

interrupt condition clearing 86 interrupt condition clear registers

for CPPI interrupt conditions 135, 137 for doorbell interrupt conditions 133

for error, reset, and special event (port) interrupt

conditions 143
for LSU interrupt conditions	141
interrupt condition routing 93
interrupt conditions 85
interrupt condition status checking		86
interrupt condition status registers
for CPPI interrupt conditions	134, 136
for doorbell interrupt conditions		132

for error, reset, and special event (port) interrupt conditions 142

interrupt destinations

controlling interrupt pacing with interrupt rate control registers 99

narrowing down interrupt sources with help from
interrupt status decode registers			97
selecting with interrupt condition routing registers 93
interrupt error at port n
reporting enable field 237
status field	237
interrupt generation 99
interrupt handling 100
interrupt pacing (rate control)		99
interrupt rate control registers		154
interrupt request field for LSUn		159
interrupt status decode registers
description	150
introduction	97
mapping example 98
invert polarity bit for SERDES receiver 126
invert polarity bit for SERDES transmitter 128
INVPAIR field of SERDES_CFGRXn_CNTL				125
INVPAIR field of SERDES_CFGTXn_CNTL				128
I/O error response at LSU
reporting enable field 212
status field	210
IP_PRESCAL	233
IRQ_EN field of SPn_CTL_INDEP			236
IRQ_ERR field of SPn_CTL_INDEP			236

L

L2 memory in Load/Store module data flow diagram		39
lane select field for port n 206
large common transport system base device ID 193
large common transport system support field 186
LB field of SERDES_CFGn_CNTL 130
LCL_CFG_BAR 192
LCL_CFG_HBAR 191
LETTER_MASK field of RXU_MAP_Ln 178
LETTER field of RXU_MAP_Ln 178
letter number associated with logical/transport error		217
letter number masking	45
letters and mailboxes	43

SPRUE13A –September 2006

Submit Documentation Feedback