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SRIO Registers
Table 57. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field
Descriptions (continued)
Bit | Field | Value | Description |
LOS |
| Loss of signal. Enables loss of signal detection with 2 selectable thresholds. | |
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| 00b | Disabled. Loss of signal detection disabled. |
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| 01b | High threshold. Loss of signal detection threshold in the range 85 to 195mVdfpp. |
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| This setting is suitable for Infiniband. |
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| 10b | Low threshold. Loss of signal detection threshold in the range 65 to 175mVdfpp. |
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| This setting is suitable for |
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| 11b | Reserved |
ALIGN |
| Symbol alignment. Enables internal or external symbol alignment. | |
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| 00b | Alignment disabled. No symbol alignment will be performed while this setting is |
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| selected, or when switching to this selection from another. |
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| 01b | Comma alignment enabled. Symbol alignment will be performed whenever a |
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| misaligned comma symbol is received. |
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| 10b | Alignment jog. The symbol alignment will be adjusted by one bit position when this |
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| mode is selected (that is, the ALIGN value changes from 0xb to 1xb). |
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| 11b | Reserved |
11 | Reserved | 0 | This |
TERM | 001b | Input termination. The only valid value for this field is 001b. This value sets the | |
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| common point to 0.8 VDDT and supports AC coupled systems using CML |
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| transmitters. The transmitter has no effect on the receiver common mode, which is |
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| set to optimize the input sensitivity of the receiver. Common mode termination is |
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| via a 50 pF capacitor to VSSA. |
7 | INVPAIR |
| Invert polarity. Inverts polarity of RIORXn and RIORXn. |
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| 0 | Normal polarity. RIORXn is considered to be positive data and RIORXn negative. |
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| 1 | Inverted polarity. RIORXn is considered to be negative data and RIORXn positive. |
RATE |
| Operating rate. Selects full, half, or quarter rate operation. | |
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| 00b | Full rate. Two data samples taken per PLL output clock cycle. |
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| 01b | Half rate. One data sample taken per PLL output clock cycle. |
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| 10b | Quarter rate. One data sample taken every two PLL output clock cycles. |
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| 11b | Reserved |
BUSWIDTH | 000b | Bus width. Always write 000b to this field, to indicate a | |
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| the clock. All other values are reserved. See Section 2.3.2.1 for an explanation of |
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| the bus. |
1 | Reserved | 0 | Always write 0 to this reserved bit. |
0 | ENRX |
| Enable receiver |
|
| 0 | Disable this receiver. |
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| 1 | Enable this receiver. |
Table 58. EQ Bits
| Low Freq Gain | Zero Freq (at e28 (min)) |
0000b | Maximum | – |
0001b | Adaptive | Adaptive |
001xb |
| Reserved |
01xxb |
| Reserved |
126 | Serial RapidIO (SRIO) | SPRUE13A |