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SRIO Registers
5.78 Logical/Transport Layer Address Capture CSR (ADDR_CAPT)
The logical/transport layer address capture CSR (ADDR_CAPT) is shown in Figure 141 and described in Table 154.
Figure 141. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) - Address Offset 2014h
31 |
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| 16 |
ADDRESS_31_3 |
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15 | 3 | 2 | 1 | 0 |
ADDRESS_31_3 |
| Reserved |
| XAMSBS |
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LEGEND: R/W = Read/Write; R = Read only; |
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Table 154. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Field Descriptions
Bit | Field | Value | Description |
ADDRESS_31_3 | 00000000h | Least significant 29 bits of the address associated with the error | |
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| to |
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| 1FFFFFFFh |
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2 | Reserved | 0 | This |
XAMSBS | Extended address bits of the address associated with the error |
SPRUE13A | Serial RapidIO (SRIO) | 215 |
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