Texas Instruments TMS320TCI648x manual RapidIO Interconnect Architecture

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Overview

1.1.2RapidIO Interconnect Architecture

The interconnect architecture is defined as a packet switched protocol independent of a physical layer implementation. Figure 2 illustrates the interconnection system.

Figure 2. RapidIO Interconnect Architecture

Host￿Subsystem

Memory Memory

Host	Host
Processor	Processor

RapidIO

RapidIO

RapidIO

Switch

I/O￿Control￿Subsystem

Control	ASIC/FPGA
Processor

Memory	RapidIO
	Switch
	RapidIO
	RapidIO
	RapidIO
	Switch

InfiniBand™ HCA

IO

ProcessorMemory

To￿System Area

Network

RapidIO￿to

InfiniBand

RapidIO

Backplane

RapidIO

Switch

RapidIO

DSP DSP DSP

DSP

		RapidIO
		RapidIO
Memory	Comm	Memory	Comm
	Processor		Processor
		TDM,GMII,￿Utopia

RapidIO￿to

PCI￿Bridge

PCI

Legacy

DSP Farm Communications￿Subsystem

PCI￿Subsystem

(1)InfiniBand™ is a trademark of the InfiniBand Trade Association.

1.1.3Physical Layer 1x/4x LP-Serial Specification

Currently, there are two physical layer specifications recognized by the RapidIO Trade Association: 8/16 LP-LVDS and 1x/4x LP-Serial. The 8/16 LP-LVDS specification is a point-to-point synchronous clock sourcing DDR interface. The 1x/4x LP-Serial specification is a point-to-point, AC coupled, clock recovery interface. The two physical layer specifications are not compatible.

SRIO complies with the 1x/4x LP-Serial specification. The serializer/deserializer (SERDES) technology in SRIO also aligns with that specification.

The RapidIO Physical Layer 1x/4x LP-Serial Specification currently covers three frequency points: 1.25, 2.5, and 3.125 Gbps. This defines the total bandwidth of each differential pair of I/O signals. An 8-bit/10-bit encoding scheme ensures ample data transitions for the clock recovery circuits. Due to the 8-bit/10-bit encoding overhead, the effective data bandwidth per differential pair is 1.0, 2.0, and 2.5 Gbps respectively. Serial RapidIO only specifies these rates for both the 1x and 4x ports. A 1x port is defined as 1 TX and 1 RX differential pair. A 4x port is a combination of four of these pairs. This document describes a 4x RapidIO port that can also be configured as four 1x ports, thus providing a scalable interface capable of supporting a data bandwidth of 1 to 10 Gbps.

Figure 3 shows how to interface two 1x devices and two 4x devices. Each positive transmit data line (TDx) on one device is connected to a positive receive data line (RDx) on the other device. Likewise, each negative transmit data line (TDx) is connected to a negative receive data line (RDx).

18 Serial RapidIO (SRIO) SPRUE13A –September 2006

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