Interrupt Generation | Texas Instruments TMS320TCI648x guide

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Interrupt Conditions

Figure 61. Example Diagram of Interrupt Status Decode Register Mapping

The following are suggestions for minimizing the number of register reads to identifying the interrupt source:

∙Dedicate each doorbell ICSR to one core. The CPU can then determine the interrupt source from a single read of the decode register.

∙Assign the RX and TX CPPI queues orthogonally to different cores. The CPU can then determine the interrupt source from a single read of the decode registers. The only exceptions to this are bits 31 and 30, which are also logically ORed with LSU and port interrupt sources.

4.6Interrupt Generation

Interrupts are triggered on a 0-to-1 logic-signal transition. Regardless of the interrupt sources, the physical interrupts are set only when the total number of set ICSR bits transitions from none to one or more. The peripheral is responsible for setting the correct bit within the ICSR. The ICRR register maps the pending interrupt request to the appropriate physical interrupt line. The corresponding CPU is interrupted and reads the ISDR and ICSR registers to determine the interrupt source and appropriate action. Interrupt generation is governed by the interrupt pacing discussed Section 4.7.

4.7Interrupt Pacing

The rate at which an interrupt can be generated is controllable for each physical interrupt destination. Rate control is implemented with a programmable down-counter. The load value of the counter is written by the CPU into the appropriate interrupt rate control register (see Figure 62). The counter reloads and

SPRUE13A –September 2006

Serial RapidIO (SRIO)

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Texas Instruments TMS320TCI648x manual Interrupt Generation, Interrupt Pacing

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticsr Port Link Maintenance Request CSR n SP n Lmreq List of Figures INTDSTnRATECNTL Interrupt Rate Control Register Transmit Cppi Supported Flow Mask Registers Port-Write-In Capture CSRs List of Tables PF16BCNTL Registers LSUnREG6 Registers and the Associated LSUs SP n Errdet Registers and the Associated Ports Read This First Trademarks RapidIO Architectural Hierarchy General RapidIO System Overview RapidIO Interconnect Architecture Physical Layer 1x/4x LP-Serial Specification Features Supported in Srio Peripheral RapidIO Feature Support in Srio TI Devices Supported By This Document Features Not SupportedStandards External Devices Requirements TI Devices Supported By This Document Registers Checked For Multicast DeviceID OverviewPeripheral Data Flow Registers Checked for Multicast DeviceID Operation Sequence Srio Packets Example Packet Streaming Write Operation Sequence 4x RapidIO Packet Data Stream Streaming-Write Class Control Symbols Ftype Ttype Packet Type Srio PinsSrio Packet Type Packet Types Component Block Diagram Functional OperationPin Description Srio Component Block Diagram Serdes Macro and its Configurations Enabling the PLLMPY Enpll MPY Bit Field Value Description Enabling the Receiver Line Rate versus PLL Output Clock FrequencyEffect of the Rate Bits Frequency Range versus MPY Value CDR LOS Align Term Invpair Rate Buswidth EnrxBit Field LOS EQ Bits Enabling the TransmitterCFGRX22-19 DE Bits DE Bits of SERDESCFGTXnCNTLSwing Amplitude Reduction Swing Bits Serdes Configuration ExampleSwing Bits of SERDESCFGTXnCNTL Direct I/O Operation LSU Register Field RapidIO Packet Header Field LSU Control/Command Register Fields LSU Status Register Fields LSU Register Field FunctionBSY LSU Registers Timing Detailed Data Path Description Example Burst Nwriter Write Transactions Direct I/O TX Operation Read Transactions Direct I/O RX Operation Segmentation Message Passing Reset and Power Down State Cppi RX Scheme for RapidIO RX Operation Message Request Packet Bit Name Description RX DMA State Completion Pointer CP Address Offset 680h-6BChMailbox to Queue Mapping Register L n Rxumapl n Mailbox to Queue Mapping Register H n Rxumaph n Field Description RX Buffer Descriptor Field Descriptions DSP core uses this bit to reclaim buffers RX Cppi Mode Explanation Srio Functional Description TX Operation Cppi Boundary Diagram TX Buffer Descriptor Field Definitions TX DMA State Completion Pointer CP Address Offset 58h-5BCh Field Description TX Buffer Descriptor Field Definitions Ssize Srio Functional Description TXQUEUECNTL3 Address Offset 7ECh TXQUEUECNTL0 Address Offset 7E0hTXQUEUECNTL1 Address Offset 7E4h TXQUEUECNTL2 Address Offset 7E8h TXQUEUECNTL23-0 TXQUEUECNTL13-0TXQUEUECNTL17-4 TXQUEUECNTL111-8 TXQUEUECNTL33-0 TXQUEUECNTL37-4TXQUEUECNTL311-8 Reset and Power Down State Message Passing Software Requirements RX OperationTX Operation Initialization Example Queue MappingRX Buffer Descriptor TX Buffer Descriptor RX Buffer Descriptors Maintenance Start Message PassingDoorbell Operation Bit LSUnREG5 Examples of Doorbellinfo Designations See FigureInfo Field Segments Reg # Congestion Control Atomic Operations Detailed Description FL9 FL8 FL7 FL6 FL5 FL4 FL3 FL2 FL1 FL0 Flowcntlid FL9 Endianness Endian Conversion TMS320TCI6482 Translation for MMR space Logical Block Reset and Power DownReset Hierarchy Bus Enable and Enable Status Registers Reset and Power Down Summary Global Enable and Global Enable Status Field Descriptions Valu Description e Block Enable and Block Enable Status Field DescriptionsEnstat RegisterBit Field Peren Soft Free Software Shutdown DetailsEmulation Peripheral Control Register PCR Field Descriptions Peripheral Control Register PCR Field Descriptions TX Buffers, Credit, and Packet ReorderingMultiple Ports With 1x Operation Unavailable Outbound Credit Single Port With 1x or 4x Operation Port Mode Register Settings Enabling the Srio Peripheral13.2 PLL, Ports, Device ID and Data Rate Initializations Set Device ID Registers Peripheral Initializations Read register to check portx1-4 OK bit Assert the Peren bit to enable logical layer data flowBootload Capability Configuration and Operation Bootload Data Movement Device WakeupRX Multicast Support 16BITDEVIDUPBOUND 16BITDEVIDLOWBOUND Multicast DeviceID OperationDaisy Chain Operation and Packet Forwarding Enabling Multicast and Packet Forwarding 8BITDEVIDLOWBOUND OutboundPort 8BITDEVIDUPBOUND For the MAU or the RXU For an LSU or the TXU Unsolicitedrspns MsgreqtimeoutPktrspnstimeout Rxiodmaaccess General Description CPU Interrupts Interrupt Condition Status and Clear Registers Doorbell Interrupt Condition Status and Clear Registers Interrupt Condition Status and Clear Bits Cppi Interrupt Condition Status and Clear Registers Doorbell 2 Interrupt Condition Status and Clear Registers LSU Interrupt Condition Status and Clear Registers RX Cppi Interrupt Condition Status and Clear Registers LSU2 Bit Associated LSU Interrupt ConditionLSU4 LSU3 ICC2 ICC1 ICC0 ICS11 ICS10 ICS9 ICS8ICS2 ICS1 ICS0 ICC11 ICC10 ICC9 ICC8 Interrupt Clearing Sequence for Special Event Interrupts Interrupt Function1st Step Nd Step 3rd Step Interrupt Function St Step Nd Step Rd Step Interrupt Condition Routing RegistersInterrupt Condition Routing Options Doorbell Interrupt Condition Routing Registers ICR15 ICR14 ICR13 ICR12 Cppi Interrupt Condition Routing RegistersICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 LSU Interrupt Condition Routing Registers TX Cppi Interrupt Condition Routing Registers ICR27 ICR26 ICR25 ICR24 ICR23 ICR22 ICR21 ICR20ICR19 ICR18 ICR17 ICR16 ICR31 ICR30 ICR29 ICR28 ICR2 ICR1 ICR0 Interrupt Status Decode Registers Interrupt Status Decode Register INTDSTnDECODE Interrupt Pacing Interrupt Generation INTDSTnRATECNTL Interrupt Rate Control Register Interrupt Handling 101 Introduction Serial RapidIO Srio RegistersOffset Acronym Register Description Offset Acronym Register Description Serial RapidIO Srio Registers INTDST6DECODE INTDST3DECODEINTDST4DECODE INTDST5DECODE QUEUE1TXDMAHDP QUEUE2RXDMACP QUEUE15RXDMAHDPQUEUE0RXDMACP QUEUE1RXDMACP RXUMAPH8 RXUMAPL7RXUMAPH7 RXUMAPL8 RXUMAPH31 RXUMAPL30RXUMAPH30 RXUMAPL31 SP1CTL SP2SILENCETIMER SpipdiscoverytimerSP0SILENCETIMER SP1SILENCETIMER Class REV Peripheral Identification Register PIDPeripheral ID Register PID Field Descriptions Type Halts Peripheral Control Register PCR Peripheral Settings Control Register Persetcntl Prescalerselect Enable Serdes PLL Peripheral Global Enable Register Gblen Field Descriptions Peripheral Global Enable Register Gblen Peripheral Global Enable Status Register Gblenstat MMRs for the Srio peripheral Register Address Offset Associated Block Block n Enable Register BLKnENBlock n Enable Registers and the Associated Blocks Block n Enable Register BLKnEN Field Descriptions Block n Enable Status Registers and the Associated Blocks Block n Enable Status Register BLKnENSTAT 16BNODEID RapidIO DEVICEID1 Register DEVICEIDREG1RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions 8BNODEID RapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions RapidIO DEVICEID2 Register DEVICEIDREG2 Register Address Offset PF16BCNTL Registers PF8BCNTL Registers Packet Forwarding Register n for 8-Bit Device IDs PF8BCNTLn Register Address Offset Associated Port SERDESCFGRXnCNTL Registers and the Associated Ports Via a 50 pF capacitor to Vssa 127 SERDESCFGTXnCNTL Registers and the Associated Ports SERDESCFGTX3CNTLSwing Invpair Rate Buswidth Entx 129 SERDESCFGnCNTL Registers and the Associated Ports Serdes Macro Configuration Register n SERDESCFGnCNTL 131 Doorbell nICSR Registers DOORBELLn Interrupt Condition Status Register DOORBELLnICSR Doorbell nICCR Registers DOORBELLn Interrupt Condition Clear Register DOORBELLnICCR RX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Clear Register Rxcppiiccr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Clear Register Txcppiiccr ICS31 LSU Interrupt Condition Status Register Lsuicsr 139 140 LSU Interrupt Condition Clear Register Lsuiccr 31-17 Reserved These reserved bits return 0s when read Errrstevnticcr Field Descriptions Field Value Description Doorbell nICRR Registers = 0 to Eight interrupt destinations INTDST0-INTDST7 146 LSU Interrupt Condition Routing Registers LSUICRR0-LSUICRR3 LSU Interrupt Condition Routing Register Field Descriptions = 0 to 2, 8 to 11, Interrupt destinations INTDST0-INTDST7 Destination Interrupt Status Decode Register INTDSTnDECODE TX buffer descriptor queue 4 bit 4 of Txcppiicsr ∙ Doorbell 0, bit 15 bit 15 of DOORBELL0ICSR ISD3 ISD2ISD1 Countdownvalue INTDSTn Interrupt Rate Control Register INTDSTnRATECNTL Addressmsb LSUn Control Register 0 LSUnREG0LSUnREG0 Registers and the Associated LSUs LSUn Control Register 0 LSUnREG0 Field Descriptions LSUn Control Register 1 LSUnREG1 Field Descriptions For packet type 8 maintenance packetLSUn Control Register 1 LSUnREG1 LSUnREG1 Registers and the Associated LSUs Dspaddress LSUn Control Register 2 LSUnREG2LSUnREG2 Registers and the Associated LSUs LSUn Control Register 2 LSUnREG2 Field Descriptions Bytecount LSUn Control Register 3 LSUnREG3LSUnREG3 Registers and the Associated LSUs LSUn Control Register 3 LSUnREG3 Field Descriptions LSUn Control Register 4 LSUnREG4 LSUnREG4 Registers and the Associated LSUsLSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 5 LSUnREG5 LSUnREG5 Registers and the Associated LSUsLSUn Control Register 5 LSUnREG5 Field Descriptions Completioncode BSY LSUn Control Register 6 LSUnREG6LSUnREG6 Registers and the Associated LSUs LSUn Control Register 6 LSUnREG6 Field Descriptions LSUnFLOWMASKS Registers and the Associated LSUs LSUn Congestion Control Flow Mask Register LSUnFLOWMASKS LSU n supports Flow 8 from table entry Register QUEUEnTXDMAHDP Registers QUEUEnTXDMACP Registers QUEUEnRXDMAHDP Registers Rxcp QUEUEnRXDMACP Registers Transmit Queue Teardown Register Txqueueteardown Txcppiflowmasks Registers and the Associated TX Queues TX Queue n Flowmask Field Descriptions Queue n supports Flow 12 from table entry Receive Queue Teardown Register Rxqueueteardown Receive Cppi Control Register Rxcppicntl Field Descriptions Receive Cppi Control Register Rxcppicntl TXQUEUECNTL3 Address Offset 07ECh TXQUEUECNTL0 Address Offset 07E0hTXQUEUECNTL1 Address Offset 07E4h TXQUEUECNTL2 Address Offset 07E8h Field Pair TXQUEUECNTL211-8 Mailbox to Queue Mapping Registers RXUMAPLn and RXUMAPHn 0890h Mapper Letter LettermaskFor a single-segment message For a multi-segment message Segmentmapping Queueid Flowcntl n Registers Flow Control Table Entry Register n FLOWCNTLn Deviceidentity Device Identity CAR DevidDevice Identity CAR Devid Field Descriptions Deviceidentity Devicevendoridentity 31-0 Device Information CAR DevinfoDevice Information CAR Devinfo Field Descriptions Devicerev Assyidentity Assembly Identity CAR AsblyidAssembly Identity CAR Asblyid Field Descriptions Assyidentity Assyvendoridentity Assyrev Assembly Information CAR AsblyinfoAssembly Information CAR Asblyinfo Field Descriptions Extendedfeaturesptr Processing Element Features CAR Pefeat Field Descriptions Processing Element Features CAR Pefeat Source and target of an operation. All PEs shall at minimum Source Operations CAR Srcop Field Descriptions Source Operations CAR Srcop Resp Andswap Atomic Destination Operations CAR DestopDestination Operations CAR Destop Field Descriptions Read Write Streamwrite Writewith Datamess Doorbell Processing Element Logical Layer Control CSR Pellctl AddressingExtendedaddressingcontrol Local Configuration Space Base Address 0 CSR Lclcfghbar LcsbaBit Field Value Local Configuration Space Base Address 1 CSR Lclcfgbar Largebasedeviceid Base Device ID CSR BaseidBase Device ID CSR Baseid Field Descriptions Basedeviceid Hostbasedeviceid Host Base Device ID Lock CSR Hostbaseidlock Component Tag CSR Comptag Component Tag CSR Comptag Field DescriptionsComponenttag Efptr Efptr Efid Port Link Timeout Control CSR Spltctl Field Descriptions TimeoutvaluePort Link Time-Out Control CSR Spltctl Port Response Time-Out Control CSR Sprtctl Port General Control CSR Spgenctl Field Descriptions Port General Control CSR Spgenctl SP2LMREQ Port Link Maintenance Request CSR n SPnLMREQCommand SPnLMREQ Registers and the Associated Ports SPnLMRESP Registers and the Associated Ports Port Link Maintenance Response CSR n SPnLMRESP SPnACKIDSTAT Registers and the Associated Ports Port Local AckID Status CSR n SPnACKIDSTAT Port Error and Status CSR n SPnERRSTAT Port Error and Status CSR n SPnERRSTAT Field DescriptionsSPnERRSTAT Registers and the Associated Ports Inputerrorstp OutputerrorencOutputerrorstp Inputerrorenc Portuninitialized Portok Port Control CSR n SPnCTL SPnCTL Registers and the Associated PortsPort Control CSR n SPnCTL Field Descriptions Errorcheckdisable PortdisableOutputportenable Inputportenable Rather than a parallel port Error Reporting Block Header Register Errrptbh Logical/Transport Layer Error Detect CSR Errdet RX I/O DMA access error Logical/Transport Layer Error Enable CSR Erren Rxcppisecurityenable PktresptimeoutenableUnsolicitedrespenable Unsupportedtransenable ADDRESS6332 Logical/Transport Layer High Address Capture CSR Haddrcapt Logical/Transport Layer Address Capture CSR Addrcapt ADDRESS313Xamsbs Msbdestid Logical/Transport Layer Device ID Capture CSR IdcaptMsbdestid Destid Msbsourceid Sourceid Ftype Logical/Transport Layer Control Capture CSR CtrlcaptFtype Ttype Msginfo Impspecific Deviceid Port-Write Target Device ID CSR PwtgtidPort-Write Target Device ID CSR Pwtgtid Field Descriptions Deviceidmsb Port Error Detect CSR n SPnERRDET Port Error Detect CSR n SPnERRDET Field DescriptionsSPnERRDET Registers and the Associated Ports Rcvdpktnotaccpt ProtocolerrorDelineationerror Linktimeout Port Error Rate Enable CSR n SPnRATEEN Port Error Rate Enable CSR n SPnRATEEN Field DescriptionsSPnRATEEN Registers and the Associated Ports Pktunexpectedackiden ProtocolerrorenDelineationerroren Linktimeouten SPnERRATTRCAPTDBG0 Registers and the Associated Ports Port n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 SPnERRCAPTDBG1 Registers and the Associated Ports Port n Error Capture CSR 1 SPnERRCAPTDBG1Description Case of a control-symbol error Case of a packet error SPnERRCAPTDBG2 Registers and the Associated Ports Port n Error Capture CSR 2 SPnERRCAPTDBG2 SPnERRCAPTDBG3 Registers and the Associated Ports Port n Error Capture CSR 3 SPnERRCAPTDBG3 SPnERRCAPTDBG4 Registers and the Associated Ports Port n Error Capture CSR 4 SPnERRCAPTDBG4 Port Error Rate CSR n SPnERRRATE Port Error Rate CSR n SPnERRRATE Field DescriptionsSPnERRRATE Registers and the Associated Ports SPnERRTHRESH Registers and the Associated Ports Port Error Rate Threshold CSR n SPnERRTHRESH Pwtimer Discoverytimer Port IP Mode CSR Spipmode Field Descriptions Port IP Mode CSR Spipmode Pwirq RstenRstcs Pwen Port IP Prescaler Register Ipprescal Port IP Prescaler Register Ipprescal Field DescriptionsPrescale Port-Write-In Capture CSR Field Descriptions Port-Write-In Capture CSRs SPIPPWINCAPT0-3 Portid Port Reset Option CSR n SPnRSTOPTPort Reset Option CSR n SPnRSTOPT Field Descriptions SPnRSTOPT Registers and the Associated Ports SPnCTLINDEP Registers and the Associated Ports Port Control Independent Register n SPnCTLINDEP Maxretryen SenddbgpktIlltransen Illtranserr Port Silence Timer n Register SPnSILENCETIMER SPnSILENCETIMER Registers and the Associated PortsSilencetimer SPnMULTEVNTCS Registers and the Associated Ports MultevntcsBit Field Value Description 31-0 STYPE0 Port Control Symbol Transmit n Register SPnCSTXSPnCSTX Registers and the Associated Ports STYPE0 PAR0 PAR1 STYPE1 CMD Csemb Index Comptag Ctrlcapt Devinfo Pellctl Haddrcapt Lsuicsr 237 Pefeat 232 Srio Registers Rxcppicntl Rxcppiiccr Rxcppiicrr RXCPPIICRR2 Rxcppiicsr Broken link Degraded link Maximum retry error at port n Txqueueteardown Xoff Xon Important Notice