![](/images/new-backgrounds/1192952/192952293x1.webp)
www.ti.com
SRIO Registers
5.29 LSU Interrupt Condition Routing Registers (LSU_ICRR0–LSU_ICRR3)
Figure 90 shows the ICRRs for the LSU interrupt requests, and Table 81 shows the general description for an ICRx field in any of the four registers. These registers route LSU interrupt requests from LSU_ICSR to interrupt destinations. For example, if ICS4 = 1 in LSU_ICSR and ICR4 = 0000b in LSU_ICRR0, LSU1 has generated a transaction-timeout interrupt request, and that request is routed to interrupt destination 0. For additional programming see Section 4.4.1.2.
Figure 90. LSU Interrupt Condition Routing Registers
LSU Interrupt Condition Routing Register 0 (LSU_ICRR0) (Address Offset 02E0h)
31 | 28 | 27 | 24 | 23 | 20 | 19 | 16 |
ICR7 |
| ICR6 |
| ICR5 |
|
| ICR4 |
|
|
|
| ||||
15 | 12 | 11 | 8 | 7 | 4 | 3 | 0 |
ICR3 |
| ICR2 |
| ICR1 |
|
| ICR0 |
|
|
|
| ||||
LSU Interrupt Condition Routing Register 1 (LSU_ICRR1) (Address Offset 02E4h) |
|
|
| ||||
31 | 28 | 27 | 24 | 23 | 20 | 19 | 16 |
ICR15 |
| ICR14 |
| ICR13 |
|
| ICR12 |
|
|
|
| ||||
15 | 12 | 11 | 8 | 7 | 4 | 3 | 0 |
ICR11 |
| ICR10 |
| ICR9 |
|
| ICR8 |
|
|
|
| ||||
LSU Interrupt Condition Routing Register 2 (LSU_ICRR2) (Address Offset 02E8h) |
|
|
| ||||
31 | 28 | 27 | 24 | 23 | 20 | 19 | 16 |
ICR23 |
| ICR22 |
| ICR21 |
|
| ICR20 |
|
|
|
| ||||
15 | 12 | 11 | 8 | 7 | 4 | 3 | 0 |
ICR19 |
| ICR18 |
| ICR17 |
|
| ICR16 |
|
|
|
|
LSU Interrupt Condition Routing Register 3 (LSU_ICRR3) (Address Offset 02ECh)
31 | 28 | 27 | 24 | 23 | 20 | 19 | 16 |
| ICR31 |
| ICR30 | ICR29 |
|
| ICR28 |
|
|
|
| ||||
15 | 12 | 11 | 8 | 7 | 4 | 3 | 0 |
| ICR27 |
| ICR26 | ICR25 |
|
| ICR24 |
|
|
|
|
LEGEND: R/W = Read/Write;
SPRUE13A | Serial RapidIO (SRIO) | 147 |
Submit Documentation Feedback |
|
|