Texas Instruments TMS320TCI648x manual Srio Registers

PW_DIS field of SP_IP_MODE 231 PW_EN field of SP_IP_MODE 231 PW_IRQ field of SP_IP_MODE 231 PW_TGT_ID 218

PW_TIMER field of SP_IP_DISCOVERY_TIMER 230

Q

QUEUE_ID field of RXU_MAP_Hn 178

QUEUEn_FLOW_MASK fields of TX_CPPI_FLOW_MASKS[0–7] 169

QUEUEn_IN_ORDER fields of RX_CPPI_CNTL 173

QUEUEn_RXDMA_CP 167
QUEUEn_RXDMA_HDP 166
QUEUEn_TEAR_DWN fields of
RX_QUEUE_TEAR_DOWN 172
QUEUEn_TEAR_DWN fields of
TX_QUEUE_TEAR_DOWN 168
QUEUEn_TXDMA_CP 165
QUEUEn_TXDMA_HDP 164
queue n receive DMA completion pointer register	167
queue n receive DMA head descriptor pointer register
166
queue n transmit DMA completion pointer register	165

queue n transmit DMA head descriptor pointer register

164
Queue Pointer fields of TX_QUEUE_CNTLn	174
queue teardown bits for message reception	172
queue teardown bits for message transmission 168
queue transmission order 54

R

RapidIO
architectural hierarchy 16
external device requirements 20
features 16
features supported in SRIO peripheral		19
interconnect architecture 18
standards 20
RapidIO DEVICEID1 register	121
RapidIO DEVICEID2 register	122
RATE fields
effect on data rate 30
RATE field of SERDES_CFGRXn_CNTL			125
RATE field of SERDES_CFGTXn_CNTL			128
rate select field for SERDES receiver 126
rate select field for SERDES transmitter		128
RCVD_PKT_NOT_ACCPT field of SPn_ERR_DET				219
RCVD_PKT_OVER_276B field of SPn_ERR_DET				219

RCVD_PKT_WITH_BAD_CRC field of SPn_ERR_DET 219

RCVED_PKT_NOT_ACCPT_EN field of SPn_RATE_EN 221

RCVED_PKT_OVER_276B_EN field of SPn_RATE_EN 221

RCVED_PKT_WITH_BAD_CRC_EN field of SPn_RATE_EN 221

READ field of DEST_OP 189 READ field of SRC_OP 188

SPRUE13A –September 2006

											SRIO Registers
read support for destination device									189
read support for source device								188
READ transactions during direct I/O transmission														41
receive CPPI control register							173
receive CPPI interrupt condition clear register												135
receive CPPI interrupt condition routing registers													145
receive CPPI interrupt condition status register													134
receive queue teardown register								172
receiver enabling for SERDES macro
introduction	30
receiver enable bit				126
receive/transmit lockout field for port n										207
register configuration offset field for LSUn											156
register introduction			102
reinitialization process field for port n										236
related documentation					14
reordering of outbound packets								75
reporting thresholds for port n errors
broken link case			229
degraded link case				229
request packets
Ftypes and Ttypes				25
in SRIO operation sequence								22
requirements for external devices									20
reset and power down					70
CPPI module		59
enable and enable status registers										71
Load/Store module				43
software shutdown details						74
reset interrupt enable field for ports									232
reset interrupt status field for ports									232
reset option CSR for port n						235
RESPONSE_VALID field of SPn_LM_RESP												201
response packets
Ftypes and Ttypes				25
in SRIO operation sequence								22
responses to CPPI (message) transmissions												58
response time-out error at LSU or TXU
reporting enable field					213
status field	211
response timer
in direct I/O reception					42
in Load/Store module data flow diagram											39
in message reception					47
in message transmission						59
RETRANSMIT_SUPPRESS field of PE_FEAT												186
retry_count field of TX buffer descriptor 52
RETRY response in message passing										43
REV field of PID		111
RIOCLK and RIOCLK signals							25
RIORXn and RIORXn signals							25
RIOTXn and RIOTXn signals							25
round-robin access to TX buffer descriptor queues														54
routing interrupt conditions to interrupt destinations														93
routing registers
for CPPI interrupt conditions								145, 146
												Index			251

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