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SRIO Functional Description
Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field
Descriptions (continued)
| Bit | Field | Value | Description |
| Reserved | 00b | Always write 0s to these reserved bits. | |
| 23 | Reserved | 0 | This |
| EQ | Equalizer. Enables and configures the adaptive equalizer to compensate for loss | ||
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| in the transmission media. For the selectable values, see Table 10. |
| CDR |
| Clock/data recovery. Configures the clock/data recovery algorithm. | |
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| 000b | First order. Phase offset tracking up to ±488 ppm. |
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| 001b | Second order. Highest precision frequency offset matching but poorest response |
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| to changes in frequency offset, and longest lock time. Suitable for use in systems |
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| with fixed frequency offset. |
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| 010b | Second order. Medium precision frequency offset matching, frequency offset |
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| change response, and lock time. |
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| 011b | Second order. Best response to changes in frequency offset and fastest lock time, |
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| but lowest precision frequency offset matching. Suitable for use in systems with |
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| spread spectrum clocking. |
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| 100b | First order with fast lock. Phase offset tracking up to ±1953 ppm in the presence of |
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| ..10101010.. training pattern, and ±448 ppm otherwise. |
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| 101b | Second order with fast lock. As per setting 001, but with improved response to |
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| changes in frequency offset when not close to lock. |
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| 110b | Second order with fast lock. As per setting 010, but with improved response to |
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| changes in frequency offset when not close to lock. |
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| 111b | Second order with fast lock. As per setting 011, but with improved response to |
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| changes in frequency offset when not close to lock. |
| LOS |
| Loss of signal. Enables loss of signal detection with 2 selectable thresholds. | |
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| 00b | Disabled. Loss of signal detection disabled. |
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| 01b | High threshold. Loss of signal detection threshold in the range 85 to 195mVdfpp. |
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| This setting is suitable for Infiniband. |
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| 10b | Low threshold. Loss of signal detection threshold in the range 65 to 175mVdfpp. |
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| This setting is suitable for |
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| 11b | Reserved |
| ALIGN |
| Symbol alignment. Enables internal or external symbol alignment. | |
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| 00b | Alignment disabled. No symbol alignment will be performed while this setting is |
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| selected, or when switching to this selection from another. |
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| 01b | Comma alignment enabled. Symbol alignment will be performed whenever a |
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| misaligned comma symbol is received. |
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| 10b | Alignment jog. The symbol alignment will be adjusted by one bit position when this |
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| mode is selected (that is, the ALIGN value changes from 0xb to 1xb). |
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| 11b | Reserved |
| 11 | Reserved | 0 | This |
| TERM | 001b | Input termination. The only valid value for this field is 001b; all other values are | |
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| reserved. The value 001b sets the common point to 0.8 VDDT and supports AC |
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| coupled systems using CML transmitters. The transmitter has no effect on the |
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| receiver common mode, which is set to optimize the input sensitivity of the |
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| receiver. Common mode termination is via a 50 pF capacitor to VSSA. |
| 7 | INVPAIR |
| Invert polarity. Inverts polarity of RIORXn and RIORXn. |
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| 0 | Normal polarity. RIORXn is considered to be positive data and RIORXn negative. |
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| 1 | Inverted polarity. RIORXn is considered to be negative data and RIORXn positive. |
| RATE |
| Operating rate. Selects full, half, or quarter rate operation. | |
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| 00b | Full rate. Two data samples taken per PLL output clock cycle. |
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| 01b | Half rate. One data sample taken per PLL output clock cycle. |
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| 10b | Quarter rate. One data sample taken every two PLL output clock cycles. |
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| 11b | Reserved |
32 | Serial RapidIO (SRIO) |
| SPRUE13A |