Texas Instruments TMS320TCI648x manual Translation for MMR space, Endian Conversion TMS320TCI6482

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SRIO Functional Description

2.3.9.1Translation for MMR space

There are no Endian translation requirements for accessing the local MMR space. Regardless of the device memory Endian configuration, all configuration bus accesses are performed on 32-bit values at a fixed address position. The bit positions in the 32-bit word are defined by this specification. This means that a memory image which will be copied to a MMR is identical between Little Endian and Big Endian configurations. Configuration bus reads are performed in the same manner. Figure 30 illustrates the concept. The desired operation is to locally update a serial RapidIO MMR (offset 1000h) with a value of A0A1A2A3h, using the configuration bus.

Figure 30. Configuration Bus Example

	Byte		Byte
	lane￿0		lane￿3
L2￿offset￿0x0	A0	A1	A2	A3	DSP defined￿MMR
					offset￿0x1000
					DMA 32b

310

A0 A1 A2 A3

When accessing RapidIO defined MMR within an external device, RapidIO allows 4 bytes, 8 bytes, or any multiple of a double-word access (up to 64 bytes) for type 8 (maintenance) packets. The peripheral only supports 4-byte accesses as the target, but can generate all sizes of request packets. RapidIO is defined as Big Endian only, and has double-word aligned Big Endian packet payloads.

2.3.9.2Endian Conversion (TMS320TCI6482)

The DMA, however, supports byte wide accesses. The peripheral performs Endian conversion on the payload if Little Endian is used on the device. This conversion is not only applicable for type 8 packets, but is also relevant for all outgoing payloads of NWRITE, NWRITE_R, SWRITE, NREAD, and message packets. This means that the memory image is different between Little Endian and Big Endian configurations, as shown in Figure 31.

Figure 31. DMA Example

The￿desired￿operation￿is￿to￿send￿a￿Type￿8￿maintenance￿request￿to￿an￿external￿device. The￿goal￿is￿to￿read￿16B￿of￿RapidIO￿MMR from￿an￿external￿device,￿starting￿offset￿0x0000. This￿operation￿involves￿the￿LSU￿block￿and￿utilizes￿the￿DMA for￿transferring￿the￿response packet￿payload.

RapidIO￿defined￿bit￿positions

031

RapidIO defined

MMR offsets

MMR￿offset￿0x0000	A0	A1	A2	A3
MMR￿offset￿0x0004	B0	B1	B2	B3
MMR￿offset￿0x0008	C0	C1	C2	C3
MMR￿offset￿0x000C	D0	D1	D2	D3

Type￿8

Response

Header￿fields

A0A1A2A3B0B1B2B3￿C0C1C2C3D0D1D2D3

					Double-word0		Double-word1
Big￿Endian									Little￿Endian
Byte				Byte			Byte				Byte
address￿0			address￿3				address￿3			address￿0
L2￿offset￿0x0	A0	A1	A2	A3		L2￿offset￿0x0		A3	A2	A1	A0
L2￿offset￿0x4	B0	B1	B2	B3		L2￿offset￿0x4		B3	B2	B1	B0
L2￿offset￿0x8	C0	C1	C2	C3		L2￿offset￿0x8		C3	C2	C1	C0
L2￿offset￿0xC	D0	D1	D2	D3		L2￿offset￿0xC		D3	D2	D1	D0

SPRUE13A –September 2006 Serial RapidIO (SRIO) 69

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