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SRIO Functional Description
2.3.9.1Translation for MMR space
There are no Endian translation requirements for accessing the local MMR space. Regardless of the device memory Endian configuration, all configuration bus accesses are performed on
Figure 30. Configuration Bus Example
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L2offset0x0 | A0 | A1 | A2 | A3 |
| DSP definedMMR |
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| offset0x1000 |
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| DMA 32b |
310
A0 A1 A2 A3
When accessing RapidIO defined MMR within an external device, RapidIO allows 4 bytes, 8 bytes, or any multiple of a
2.3.9.2Endian Conversion (TMS320TCI6482)
The DMA, however, supports byte wide accesses. The peripheral performs Endian conversion on the payload if Little Endian is used on the device. This conversion is not only applicable for type 8 packets, but is also relevant for all outgoing payloads of NWRITE, NWRITE_R, SWRITE, NREAD, and message packets. This means that the memory image is different between Little Endian and Big Endian configurations, as shown in Figure 31.
Figure 31. DMA Example
ThedesiredoperationistosendaType8maintenancerequesttoanexternaldevice. Thegoalistoread16BofRapidIOMMR fromanexternaldevice,startingoffset0x0000. ThisoperationinvolvestheLSUblockandutilizestheDMA fortransferringtheresponse packetpayload.
RapidIOdefinedbitpositions
031
RapidIO defined
MMR offsets
MMRoffset0x0000 | A0 | A1 | A2 | A3 |
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MMRoffset0x0004 | B0 | B1 | B2 | B3 |
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MMRoffset0x0008 | C0 | C1 | C2 | C3 |
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MMRoffset0x000C | D0 | D1 | D2 | D3 |
Type8
Response
Headerfields
A0A1A2A3B0B1B2B3C0C1C2C3D0D1D2D3
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BigEndian |
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address0 | address3 |
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L2offset0x0 | A0 | A1 | A2 | A3 |
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| L2offset0x0 | A3 | A2 | A1 | A0 |
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L2offset0x4 | B0 | B1 | B2 | B3 |
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| L2offset0x4 | B3 | B2 | B1 | B0 |
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L2offset0x8 | C0 | C1 | C2 | C3 |
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| L2offset0x8 | C3 | C2 | C1 | C0 |
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L2offset0xC | D0 | D1 | D2 | D3 |
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| L2offset0xC | D3 | D2 | D1 | D0 |
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SPRUE13A | Serial RapidIO (SRIO) | 69 |