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SRIO Registers
5.73 Port Control CSR n (SPn_CTL)
Each of the four ports is supported by a register of this type (see Table 148). The port control CSR n (SPn_CTL) is shown in Figure 136 and described in Table 149. To change from 1 lane to 4 lanes there are 2 registers that need to be programmed. The SP_IP_MODE (offset 0x12004) bits
Table 148. SPn_CTL Registers and the Associated Ports
Register | Address Offset | Associated Port |
SP0_CTL | 115Ch | Port 0 |
SP1_CTL | 117Ch | Port 1 |
SP2_CTL | 119Ch | Port 2 |
SP3_CTL | 11BCh | Port 3 |
Figure 136. Port Control CSR n (SPn_CTL)
31 |
| 30 | 29 |
| 27 | 26 |
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| 24 |
PORT_WIDTH |
| INITIALIZED_PORT_WIDTH |
| PORT_WIDTH_OVERRIDE | |||||
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23 | 22 |
| 21 | 20 | 19 | 18 |
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| 16 |
PORT_ | OUTPUT_ |
| INPUT_ | ERROR_ | MULTICAST_ |
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PORT_ |
| PORT_ | CHECK_ |
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| Reserved |
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DISABLE |
| PARTICIPANT |
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ENABLE |
| ENABLE | DISABLE |
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15 |
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| 8 |
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| Reserved |
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7 |
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| 4 | 3 |
| 2 | 1 | 0 |
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| STOP_PORT_ |
| DROP_ | PORT_ |
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| Reserved |
| FLD_ENC_ |
| PACKET_ | PORT_TYPE | |||
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| LOCKOUT | ||||||
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| ENABLE |
| ENABLE |
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LEGEND: R/W = Read/Write; R = Read only; |
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Table 149. Port Control CSR n (SPn_CTL) Field Descriptions
Bit | Field | Value | Description |
PORT_WIDTH |
| Port width. This | |
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| the port. |
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| 00b | |
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| 01b | |
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| 1xb | Reserved |
INITIALIZED_PORT_WIDTH |
| Initialized port width. This | |
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| the ports after initialization. |
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| 000b | |
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| 001b | |
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| 4.4.10) |
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| 010b | |
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| Reserved |
206 | Serial RapidIO (SRIO) | SPRUE13A |
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