Texas Instruments TMS320TCI648x specs

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Interrupt Conditions

each bit in the ISDR. Bits within the LSU interrupt condition status register (ICSR) are logically grouped for a given core and ORed together into a single bit (bit 31) of the decode register. Similarly, the bits within the Error, Reset, and Special Event ICSR are ORed together into bit 30 of the decode register. The TX CPPI and RX CPPI interrupt sources (one for each buffer descriptor queue) can be mapped to bits 31–16 as shown in Figure 60. The doorbell interrupt sources can be mapped to bits 15–0.

An interrupt source is mapped to ISDR bits only if the ICRR for that interrupt source routes it to the corresponding interrupt destination. When multiple interrupt sources are mapped to the same bit, the bit status is a logical OR of those interrupt sources. The mapping of interrupt source bits to decode bits is fixed and is not programmable.

Figure 59. Interrupt Status Decode Register (INTDSTn_DECODE)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

ISD31

ISD30

ISD29

ISD28

ISD27

ISD26

ISD25

ISD24

ISD23

ISD22

ISD21

ISD20

ISD19

ISD18

ISD17

ISD16

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ISD15

ISD14

ISD13

ISD12

ISD11

ISD10

ISD9

ISD8

ISD7

ISD6

ISD5

ISD4

ISD3

ISD2

ISD1

ISD0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

LEGEND: R = Read only; -n= Value after reset

Figure 60. Interrupt Sources Assigned to ISDR Bits

APlease note that bits 0 through 15 of this ICSR correspond to bits 31 through 16 of the ISDR. For example, bit 15 of the ICSR corresponds to bit 31 of the ISDR, and so on.

BPlease note that bits 15 through 0 of this ICSR correspond to bits 15 through 0 of the ISDR. For example, bit 15 of the ICSR corresponds to bit 15 of the ISDR, and so on.

As an example of reading an ISDR, if bit 29 of the ISDR is set, this indicates that there is a pending interrupt on either the TX CPPI queue 2 or RX CPPI queue 2. Figure 61 illustrates the decode routing for this example.

98

Serial RapidIO (SRIO)

SPRUE13A –September 2006

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Texas Instruments TMS320TCI648x manual Interrupt Status Decode Register INTDSTnDECODE

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticsr Port Link Maintenance Request CSR n SP n Lmreq List of Figures INTDSTnRATECNTL Interrupt Rate Control Register Transmit Cppi Supported Flow Mask Registers Port-Write-In Capture CSRs List of Tables PF16BCNTL Registers LSUnREG6 Registers and the Associated LSUs SP n Errdet Registers and the Associated Ports Read This First Trademarks General RapidIO System RapidIO Architectural Hierarchy Overview Physical Layer 1x/4x LP-Serial Specification RapidIO Interconnect Architecture RapidIO Feature Support in Srio Features Supported in Srio Peripheral TI Devices Supported By This Document Features Not SupportedStandards External Devices Requirements TI Devices Supported By This Document Registers Checked for Multicast DeviceID OverviewPeripheral Data Flow Registers Checked For Multicast DeviceID Srio Packets Operation Sequence Operation Sequence Example Packet Streaming Write Control Symbols 4x RapidIO Packet Data Stream Streaming-Write Class Packet Types Srio PinsSrio Packet Type Ftype Ttype Packet Type Pin Description Component Block DiagramFunctional Operation Srio Component Block Diagram MPY Enpll Serdes Macro and its ConfigurationsEnabling the PLL Bit Field Value Description MPY Frequency Range versus MPY Value Line Rate versus PLL Output Clock FrequencyEffect of the Rate Bits Enabling the Receiver Bit Field CDRLOS Align Term Invpair Rate Buswidth Enrx LOS CFGRX22-19 EQ BitsEnabling the Transmitter Amplitude Reduction DE Bits of SERDESCFGTXnCNTLSwing DE Bits Direct I/O Operation Serdes Configuration ExampleSwing Bits of SERDESCFGTXnCNTL Swing Bits LSU Control/Command Register Fields LSU Register Field RapidIO Packet Header Field BSY LSU Status Register FieldsLSU Register Field Function LSU Registers Timing Example Burst Nwriter Detailed Data Path Description Direct I/O TX Operation Write Transactions Read Transactions Segmentation Direct I/O RX Operation Reset and Power Down State Message Passing RX Operation Cppi RX Scheme for RapidIO Message Request Packet Mailbox to Queue Mapping Register H n Rxumaph n RX DMA State Completion Pointer CP Address Offset 680h-6BChMailbox to Queue Mapping Register L n Rxumapl n Bit Name Description RX Buffer Descriptor Field Descriptions Field Description DSP core uses this bit to reclaim buffers RX Cppi Mode Explanation Srio Functional Description Cppi Boundary Diagram TX Operation TX DMA State Completion Pointer CP Address Offset 58h-5BCh TX Buffer Descriptor Field Definitions TX Buffer Descriptor Field Definitions Field Description Ssize Srio Functional Description TXQUEUECNTL2 Address Offset 7E8h TXQUEUECNTL0 Address Offset 7E0hTXQUEUECNTL1 Address Offset 7E4h TXQUEUECNTL3 Address Offset 7ECh TXQUEUECNTL111-8 TXQUEUECNTL13-0TXQUEUECNTL17-4 TXQUEUECNTL23-0 TXQUEUECNTL311-8 TXQUEUECNTL33-0TXQUEUECNTL37-4 Reset and Power Down State TX Operation Message Passing Software RequirementsRX Operation RX Buffer Descriptor Initialization ExampleQueue Mapping RX Buffer Descriptors TX Buffer Descriptor Doorbell Operation MaintenanceStart Message Passing Reg # Examples of Doorbellinfo Designations See FigureInfo Field Segments Bit LSUnREG5 Atomic Operations Congestion Control Detailed Description Flowcntlid FL9 FL8 FL7 FL6 FL5 FL4 FL3 FL2 FL1 FL0 Endianness FL9 Translation for MMR space Endian Conversion TMS320TCI6482 Bus Reset and Power DownReset Hierarchy Logical Block Reset and Power Down Summary Enable and Enable Status Registers Global Enable and Global Enable Status Field Descriptions RegisterBit Field Block Enable and Block Enable Status Field DescriptionsEnstat Valu Description e Peripheral Control Register PCR Field Descriptions Software Shutdown DetailsEmulation Peren Soft Free Multiple Ports With 1x Operation Peripheral Control Register PCR Field DescriptionsTX Buffers, Credit, and Packet Reordering Single Port With 1x or 4x Operation Unavailable Outbound Credit 13.2 PLL, Ports, Device ID and Data Rate Initializations Port Mode Register SettingsEnabling the Srio Peripheral Peripheral Initializations Set Device ID Registers Configuration and Operation Assert the Peren bit to enable logical layer data flowBootload Capability Read register to check portx1-4 OK bit RX Multicast Support Bootload Data MovementDevice Wakeup Enabling Multicast and Packet Forwarding Multicast DeviceID OperationDaisy Chain Operation and Packet Forwarding 16BITDEVIDUPBOUND 16BITDEVIDLOWBOUND 8BITDEVIDUPBOUND OutboundPort 8BITDEVIDLOWBOUND For an LSU or the TXU For the MAU or the RXU Rxiodmaaccess MsgreqtimeoutPktrspnstimeout Unsolicitedrspns CPU Interrupts General Description Interrupt Condition Status and Clear Registers Interrupt Condition Status and Clear Bits Doorbell Interrupt Condition Status and Clear Registers Doorbell 2 Interrupt Condition Status and Clear Registers Cppi Interrupt Condition Status and Clear Registers RX Cppi Interrupt Condition Status and Clear Registers LSU Interrupt Condition Status and Clear Registers LSU3 Bit Associated LSU Interrupt ConditionLSU4 LSU2 ICC11 ICC10 ICC9 ICC8 ICS11 ICS10 ICS9 ICS8ICS2 ICS1 ICS0 ICC2 ICC1 ICC0 1st Step Nd Step 3rd Step Interrupt Clearing Sequence for Special Event InterruptsInterrupt Function Doorbell Interrupt Condition Routing Registers Interrupt Condition Routing RegistersInterrupt Condition Routing Options Interrupt Function St Step Nd Step Rd Step ICR3 ICR2 ICR1 ICR0 Cppi Interrupt Condition Routing RegistersICR7 ICR6 ICR5 ICR4 ICR15 ICR14 ICR13 ICR12 TX Cppi Interrupt Condition Routing Registers LSU Interrupt Condition Routing Registers ICR31 ICR30 ICR29 ICR28 ICR23 ICR22 ICR21 ICR20ICR19 ICR18 ICR17 ICR16 ICR27 ICR26 ICR25 ICR24 Interrupt Status Decode Registers ICR2 ICR1 ICR0 Interrupt Status Decode Register INTDSTnDECODE Interrupt Generation Interrupt Pacing Interrupt Handling INTDSTnRATECNTL Interrupt Rate Control Register 101 Offset Acronym Register Description IntroductionSerial RapidIO Srio Registers Serial RapidIO Srio Registers Offset Acronym Register Description INTDST5DECODE INTDST3DECODEINTDST4DECODE INTDST6DECODE QUEUE1TXDMAHDP QUEUE1RXDMACP QUEUE15RXDMAHDPQUEUE0RXDMACP QUEUE2RXDMACP RXUMAPL8 RXUMAPL7RXUMAPH7 RXUMAPH8 RXUMAPL31 RXUMAPL30RXUMAPH30 RXUMAPH31 SP1CTL SP1SILENCETIMER SpipdiscoverytimerSP0SILENCETIMER SP2SILENCETIMER Type Peripheral Identification Register PIDPeripheral ID Register PID Field Descriptions Class REV Peripheral Control Register PCR Halts Peripheral Settings Control Register Persetcntl Prescalerselect Enable Serdes PLL Peripheral Global Enable Register Gblen Peripheral Global Enable Register Gblen Field Descriptions Peripheral Global Enable Status Register Gblenstat MMRs for the Srio peripheral Block n Enable Register BLKnEN Field Descriptions Block n Enable Register BLKnENBlock n Enable Registers and the Associated Blocks Register Address Offset Associated Block Block n Enable Status Register BLKnENSTAT Block n Enable Status Registers and the Associated Blocks 8BNODEID RapidIO DEVICEID1 Register DEVICEIDREG1RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions 16BNODEID RapidIO DEVICEID2 Register DEVICEIDREG2 RapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions PF16BCNTL Registers Register Address Offset Packet Forwarding Register n for 8-Bit Device IDs PF8BCNTLn PF8BCNTL Registers SERDESCFGRXnCNTL Registers and the Associated Ports Register Address Offset Associated Port Via a 50 pF capacitor to Vssa 127 Swing Invpair Rate Buswidth Entx SERDESCFGTXnCNTL Registers and the Associated PortsSERDESCFGTX3CNTL 129 Serdes Macro Configuration Register n SERDESCFGnCNTL SERDESCFGnCNTL Registers and the Associated Ports 131 DOORBELLn Interrupt Condition Status Register DOORBELLnICSR Doorbell nICSR Registers DOORBELLn Interrupt Condition Clear Register DOORBELLnICCR Doorbell nICCR Registers RX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Clear Register Rxcppiiccr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Clear Register Txcppiiccr LSU Interrupt Condition Status Register Lsuicsr ICS31 139 140 LSU Interrupt Condition Clear Register Lsuiccr 31-17 Reserved These reserved bits return 0s when read Errrstevnticcr Field Descriptions Doorbell nICRR Registers Field Value Description = 0 to Eight interrupt destinations INTDST0-INTDST7 146 LSU Interrupt Condition Routing Registers LSUICRR0-LSUICRR3 LSU Interrupt Condition Routing Register Field Descriptions = 0 to 2, 8 to 11, Interrupt destinations INTDST0-INTDST7 Interrupt Status Decode Register INTDSTnDECODE Destination TX buffer descriptor queue 4 bit 4 of Txcppiicsr ∙ Doorbell 0, bit 15 bit 15 of DOORBELL0ICSR ISD1 ISD3ISD2 INTDSTn Interrupt Rate Control Register INTDSTnRATECNTL Countdownvalue LSUn Control Register 0 LSUnREG0 Field Descriptions LSUn Control Register 0 LSUnREG0LSUnREG0 Registers and the Associated LSUs Addressmsb LSUnREG1 Registers and the Associated LSUs For packet type 8 maintenance packetLSUn Control Register 1 LSUnREG1 LSUn Control Register 1 LSUnREG1 Field Descriptions LSUn Control Register 2 LSUnREG2 Field Descriptions LSUn Control Register 2 LSUnREG2LSUnREG2 Registers and the Associated LSUs Dspaddress LSUn Control Register 3 LSUnREG3 Field Descriptions LSUn Control Register 3 LSUnREG3LSUnREG3 Registers and the Associated LSUs Bytecount LSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 4 LSUnREG4LSUnREG4 Registers and the Associated LSUs LSUn Control Register 5 LSUnREG5 Field Descriptions LSUn Control Register 5 LSUnREG5LSUnREG5 Registers and the Associated LSUs LSUn Control Register 6 LSUnREG6 Field Descriptions LSUn Control Register 6 LSUnREG6LSUnREG6 Registers and the Associated LSUs Completioncode BSY LSUn Congestion Control Flow Mask Register LSUnFLOWMASKS LSUnFLOWMASKS Registers and the Associated LSUs LSU n supports Flow 8 from table entry QUEUEnTXDMAHDP Registers Register QUEUEnTXDMACP Registers QUEUEnRXDMAHDP Registers QUEUEnRXDMACP Registers Rxcp Transmit Queue Teardown Register Txqueueteardown Txcppiflowmasks Registers and the Associated TX Queues TX Queue n Flowmask Field Descriptions Queue n supports Flow 12 from table entry Receive Queue Teardown Register Rxqueueteardown Receive Cppi Control Register Rxcppicntl Receive Cppi Control Register Rxcppicntl Field Descriptions TXQUEUECNTL2 Address Offset 07E8h TXQUEUECNTL0 Address Offset 07E0hTXQUEUECNTL1 Address Offset 07E4h TXQUEUECNTL3 Address Offset 07ECh Field Pair TXQUEUECNTL211-8 Mailbox to Queue Mapping Registers RXUMAPLn and RXUMAPHn 0890h Mapper For a multi-segment message LettermaskFor a single-segment message Letter Queueid Segmentmapping Flow Control Table Entry Register n FLOWCNTLn Flowcntl n Registers Deviceidentity Devicevendoridentity Device Identity CAR DevidDevice Identity CAR Devid Field Descriptions Deviceidentity Devicerev Device Information CAR DevinfoDevice Information CAR Devinfo Field Descriptions 31-0 Assyidentity Assyvendoridentity Assembly Identity CAR AsblyidAssembly Identity CAR Asblyid Field Descriptions Assyidentity Extendedfeaturesptr Assembly Information CAR AsblyinfoAssembly Information CAR Asblyinfo Field Descriptions Assyrev Processing Element Features CAR Pefeat Processing Element Features CAR Pefeat Field Descriptions Source and target of an operation. All PEs shall at minimum Source Operations CAR Srcop Source Operations CAR Srcop Field Descriptions Read Write Streamwrite Writewith Datamess Doorbell Destination Operations CAR DestopDestination Operations CAR Destop Field Descriptions Resp Andswap Atomic Extendedaddressingcontrol Processing Element Logical Layer Control CSR PellctlAddressing Bit Field Value Local Configuration Space Base Address 0 CSR LclcfghbarLcsba Local Configuration Space Base Address 1 CSR Lclcfgbar Basedeviceid Base Device ID CSR BaseidBase Device ID CSR Baseid Field Descriptions Largebasedeviceid Host Base Device ID Lock CSR Hostbaseidlock Hostbasedeviceid Componenttag Component Tag CSR ComptagComponent Tag CSR Comptag Field Descriptions Efptr Efid Efptr Port Link Time-Out Control CSR Spltctl Port Link Timeout Control CSR Spltctl Field DescriptionsTimeoutvalue Port Response Time-Out Control CSR Sprtctl Port General Control CSR Spgenctl Port General Control CSR Spgenctl Field Descriptions SPnLMREQ Registers and the Associated Ports Port Link Maintenance Request CSR n SPnLMREQCommand SP2LMREQ Port Link Maintenance Response CSR n SPnLMRESP SPnLMRESP Registers and the Associated Ports Port Local AckID Status CSR n SPnACKIDSTAT SPnACKIDSTAT Registers and the Associated Ports SPnERRSTAT Registers and the Associated Ports Port Error and Status CSR n SPnERRSTATPort Error and Status CSR n SPnERRSTAT Field Descriptions Inputerrorenc OutputerrorencOutputerrorstp Inputerrorstp Portok Portuninitialized Port Control CSR n SPnCTL Field Descriptions Port Control CSR n SPnCTLSPnCTL Registers and the Associated Ports Inputportenable PortdisableOutputportenable Errorcheckdisable Rather than a parallel port Error Reporting Block Header Register Errrptbh Logical/Transport Layer Error Detect CSR Errdet RX I/O DMA access error Logical/Transport Layer Error Enable CSR Erren Unsupportedtransenable PktresptimeoutenableUnsolicitedrespenable Rxcppisecurityenable Logical/Transport Layer High Address Capture CSR Haddrcapt ADDRESS6332 Xamsbs Logical/Transport Layer Address Capture CSR AddrcaptADDRESS313 Msbsourceid Sourceid Logical/Transport Layer Device ID Capture CSR IdcaptMsbdestid Destid Msbdestid Impspecific Logical/Transport Layer Control Capture CSR CtrlcaptFtype Ttype Msginfo Ftype Deviceidmsb Port-Write Target Device ID CSR PwtgtidPort-Write Target Device ID CSR Pwtgtid Field Descriptions Deviceid SPnERRDET Registers and the Associated Ports Port Error Detect CSR n SPnERRDETPort Error Detect CSR n SPnERRDET Field Descriptions Linktimeout ProtocolerrorDelineationerror Rcvdpktnotaccpt SPnRATEEN Registers and the Associated Ports Port Error Rate Enable CSR n SPnRATEENPort Error Rate Enable CSR n SPnRATEEN Field Descriptions Linktimeouten ProtocolerrorenDelineationerroren Pktunexpectedackiden Port n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 SPnERRATTRCAPTDBG0 Registers and the Associated Ports Case of a packet error Port n Error Capture CSR 1 SPnERRCAPTDBG1Description Case of a control-symbol error SPnERRCAPTDBG1 Registers and the Associated Ports Port n Error Capture CSR 2 SPnERRCAPTDBG2 SPnERRCAPTDBG2 Registers and the Associated Ports Port n Error Capture CSR 3 SPnERRCAPTDBG3 SPnERRCAPTDBG3 Registers and the Associated Ports Port n Error Capture CSR 4 SPnERRCAPTDBG4 SPnERRCAPTDBG4 Registers and the Associated Ports SPnERRRATE Registers and the Associated Ports Port Error Rate CSR n SPnERRRATEPort Error Rate CSR n SPnERRRATE Field Descriptions Port Error Rate Threshold CSR n SPnERRTHRESH SPnERRTHRESH Registers and the Associated Ports Discoverytimer Pwtimer Port IP Mode CSR Spipmode Port IP Mode CSR Spipmode Field Descriptions Pwen RstenRstcs Pwirq Prescale Port IP Prescaler Register IpprescalPort IP Prescaler Register Ipprescal Field Descriptions Port-Write-In Capture CSRs SPIPPWINCAPT0-3 Port-Write-In Capture CSR Field Descriptions SPnRSTOPT Registers and the Associated Ports Port Reset Option CSR n SPnRSTOPTPort Reset Option CSR n SPnRSTOPT Field Descriptions Portid Port Control Independent Register n SPnCTLINDEP SPnCTLINDEP Registers and the Associated Ports Illtranserr SenddbgpktIlltransen Maxretryen Silencetimer Port Silence Timer n Register SPnSILENCETIMERSPnSILENCETIMER Registers and the Associated Ports Bit Field Value Description 31-0 SPnMULTEVNTCS Registers and the Associated PortsMultevntcs STYPE0 PAR0 PAR1 STYPE1 CMD Csemb Port Control Symbol Transmit n Register SPnCSTXSPnCSTX Registers and the Associated Ports STYPE0 Index Comptag Ctrlcapt Devinfo Pellctl Haddrcapt Lsuicsr 237 Pefeat 232 Srio Registers Rxcppicntl Rxcppiiccr Rxcppiicrr RXCPPIICRR2 Rxcppiicsr Broken link Degraded link Maximum retry error at port n Txqueueteardown Xoff Xon Important Notice