Texas Instruments TMS320TCI648x manual RX DMA State Completion Pointer CP Address Offset 680h-6BCh

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SRIO Functional Description

Figure 18. Mailbox to Queue Mapping Register Pair

Mailbox to Queue Mapping Register L n (RXU_MAP_L n )

31	30	29	24	23	22	21	16
LETTER_MASK		MAILBOX_MASK		LETTER			MAILBOX
	R/W-11	R/W-111111		R/W-00			R/W-000000
15							0
			SOURCEID
			R/W-0000h

Mailbox to Queue Mapping Register H n (RXU_MAP_H n )

31

Reserved

R-0

10	9	8	7	6	5	2	1	0
Reserved		TT	Reserved		QUEUE_ID		PROMISCUOUS	SEGMENT
								MAPPING
R-0		R/W-01	R-00		R/W-0000		R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= Value after reset

The packet manager maintains the RX DMA state of free and used data buffers within the memory space. It directs the data to specific addresses within the memory and maintains and updates the buffer descriptor queues. There is a single buffer descriptor per RapidIO message. For example, single segment messages have one buffer descriptor, as do multi-segment messages with up to 4K-byte payloads.

There can be multiple RX buffer descriptor queues per core. It is suggested that one queue be dedicated to single segment messages and additional queues be dedicated to multi-segment messages. Each multi-segment message queue can support only one incoming message at a time. Depending on the application, it may be necessary to support multiple simultaneous segmentation and reassembly (SAR) operations per core. In this case, a buffer descriptor queue is allocated for each desired simultaneous message. The peripheral supports a total of 16 assignable RX queues and their associated RX DMA state registers. Each of the queues can be assigned to single or multi-segment messages.

Table 16 and Table 17 describe the RX DMA State Registers.

Table 16. RX DMA State Head Descriptor Pointer (HDP) (Address Offset 600h–63Ch)

Bit	Name	Description
31–0	RX Queue Head	RX Queue Head Descriptor Pointer: This field is the memory address for the first buffer descriptor
	Descriptor Pointer	in the channel receive queue. This field is written by the DSP core to initiate queue receive
		operations and is zeroed by the port when all free buffers have been used. An error condition
		results if the DSP core writes this field when the current field value is nonzero. The address must
		be 32-bit word aligned.

Table 17. RX DMA State Completion Pointer (CP) (Address Offset 680h–6BCh)

Bit	Name	Description
31–0	RX Queue	RX Queue Completion Pointer: This field is the memory address for the receive queue completion
	Completion Pointer	pointer. This register is written by the DSP core with the buffer descriptor address for the last buffer
		processed by the DSP core during interrupt processing. The port uses the value written to
		determine if the interrupt should be deasserted.

If a multi-segment buffer descriptor queue is not currently free, and an RX port receives another multi-segment message that is destined for that queue, the RX CPPI sends a RETRY RESPONSE packet (type 13) to the sender, indicating that an internal buffering problem exists. If a multi-segment buffer descriptor queue is busy and there is another incoming multi-segment message with the same SOURCEID, MAILBOX, and LETTER, an ERROR response is sent. This usually indicates that a TX programming error has occurred, where duplicate segments or segments outside the MSGLEN were sent. Upon successful reception of any message segment, the RX CPPI is responsible for sending a DONE response to the sender.

46 Serial RapidIO (SRIO) SPRUE13A –September 2006

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