SRIO Registers

 

DEV_INFO 183

 

DEVICE_VENDORIDENTITY field of DEV_ID 182

DEVICEID_MSB field of PW_TGT_ID 218

DEVICEID_REG1

121

DEVICEID_REG2

122

device ID capture CSR for logical/transport errors 216

device identity CAR

182

DEVICEIDENTITY field of DEV_ID 182

DEVICEID field of PW_TGT_ID 218

device IDs

 

base device ID for host PE 194

base device ID for large common transport system 193

base device ID for small common transport system 193

device ID for port-write target 218

disable base ID match requirement field for ports 231 flow control destination ID size field 181

lower boundary for packet forwarding

8-bit IDs 124

16-bit IDs 123

node ID field to compare to incoming destination ID 122

node ID field to supply outgoing source ID 121

size selection field for LSUn 159

 

 

upper boundary for packet forwarding

 

8-bit IDs 124

 

 

 

 

16-bit IDs

123

 

 

 

 

device information CAR

183

 

 

 

device revision field 183

 

 

 

device type field 182

 

 

 

 

device wakeup after bootloading

80

 

 

differential signals/pins

25

 

 

 

direct I/O

 

 

 

 

 

data path description

39

 

 

 

introduction

35

 

 

 

 

RX operation

42

 

 

 

 

TX operation

40

 

 

 

 

disable error checking for port n

207

 

 

disable port n

207

 

 

 

 

DISCOVERED field of SP_GEN_CTL

199

 

DISCOVERY_TIMER field of

 

 

 

SP_IP_DISCOVERY_TIMER 230

 

 

DMA bus

 

 

 

 

 

considerations regarding CPU interrupts

85

in data path description for LSUs 39

 

in direct I/O RX operation 42

 

 

 

in Load/Store module data flow diagram

39

in message passing

43

 

 

 

in SRIO component block diagram

26

 

DMA clock frequency as variable in clock prescaling

233

 

 

DMA error status bit for MAU 211

 

doorbell information field for LSUn 160

 

doorbell interrupt condition clear registers

133

doorbell interrupt condition routing registers

144

244

Index

 

doorbell interrupt condition status registers 132 DOORBELLn_ICCR 133 DOORBELLn_ICRR 144 DOORBELLn_ICRR2 144 DOORBELLn_ICSR 132

doorbell operation 63 doorbell packets

Ftype and Ttype 25 packet header 64 priority 64

used to cause CPU interrupts 85

doorbell-retry response during direct I/O reception 42 doorbell support for destination device 189

doorbell support for source device

188

DRBLL_INFO field of LSUn_REG5

160

drop packet enable for port n

207

 

DSP address field for LSUn

157

 

E

EF_ID field of ERR_RPT_BH

209

 

EF_ID field of SP_MB_HEAD

196

 

EF_PTR field of ERR_RPT_BH

209

EF_PTR field of SP_MB_HEAD

196

emulation 74

 

 

 

EN_STAT field of BLKn_EN_STAT

120

enable and enable status registers

71

enable bit(s)

for access to read-only registers during boot loading 113

for adaptive equalizer 125

 

for entire SRIO peripheral

116

 

for fixed-phase transmit clocking

128

for flow control 112

 

 

for logical blocks 119

 

 

for port idle error checking

231

 

for port illegal-transfer error reporting 237

for port multicast-event interrupt

231

for port n 207

 

 

 

for port reset interrupt 232

 

for port self-reset interrupt

231

 

for port-write error reporting 231

 

for port-write-in interrupt 232

 

for SERDES PLLs

115, 131

 

for SERDES receivers 126

 

for SERDES transmitters

129

 

enable input only for port n

207

 

enable multicast-event participation for port n 207

enable output only for port n

207

 

enable status bit(s)

 

 

 

for entire SRIO peripheral

117

 

for logical blocks 0 through 8 117, 120

endianness 68

 

 

 

EN field of BLKn_EN

119

 

 

EN field of GBL_EN

116

 

 

ENFTP field of SERDES_CFGTXn_CNTL 128

ENPLL1 field of PER_SET_CNTL

113

SPRUE13A –September 2006

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Texas Instruments TMS320TCI648x manual Devinfo