Texas Instruments TMS320TCI648x manual Example Burst Nwriter, Detailed Data Path Description

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SRIO Functional Description

Figure 14. Example Burst NWRITE_R

																									LSUn_REG2
																									DSP Address
															LSUn_REG4
									OutPortID			Priority			xambs			ID￿Size			DestID			RSV	Interrupt￿Req
								31		30	29	28		27		26	25	24		23		8	7	1	0
		LSUn_REG5
	Drbll	Hop￿Count			Packet
31	16	15	8	7		0
																													Count
																LSUn_REG0											translator
																LSUn_REG1
															RapioIO Address/Config_offset											rdsize/				rdptr/
																										wsize				wptr
															NodeID
																									Count*8
	ackID	rsv	prio		tt		ftype		destID	sourceID			trans		wrsize	srcTID			ext￿addr		address		wr￿ptr	xamsbs	payload			CRC
	5	3		2	2	4		8			8	4		4			8	32		29			1	2				16

LSUn_REG3

Byte￿Count

TX￿Shared￿Buffer￿Pool

DMA Read

Source Address

Destination Address

Count

For WRITE commands, the payload is combined with the header information from the control/command registers and buffered in the shared TX buffer resource pool. Finally, it is forwarded to the TX FIFO for transmission. READ commands have no payload. In this case, only the control/command register fields are buffered and used to create a RapidIO NREAD packet, which is forwarded to the TX FIFO. Corresponding response packet payloads from READ transactions are buffered in the shared RX buffer resource pool when forwarded from the receive ports. Both posted and non-posted operations rely on the OutPortID command register field to specify the appropriate output port/FIFO.

The data is burst internally to the Load/Store module at the DMA clock rate.

2.3.3.1Detailed Data Path Description

The Load/Store module is for generating all outgoing RapidIO direct I/O packets. Any read or write transaction, other than the messaging protocol, uses this interface. In addition, outgoing DOORBELL packets are generated through this interface.

The data path for this module uses DMA bus as the DMA interface. The configuration bus is used by the CPU to access the control/command registers. The registers contain transfer descriptors that are needed to initiate READ and WRITE packet generation. After the transfer descriptors are written, flow control status is queried. The unit examines the DESTID and PRIORITY fields of LSUn_REG4 to determine if that flow has been Xoffd. Additionally, the free buffer status of the TX FIFO is checked (based on the OutPortID register field). Only after the flow control access is granted, and a TX FIFO buffer has been allocated, can a DMA bus read command be issued for payload data to be moved into the shared TX buffer. Data is moved from the shared TX buffer to the appropriate output TX FIFO in simple sequential order based on completion of the DMA bus transaction. However, if fabric congestion occurs, priority can affect the order in which the data leaves the TX FIFOs.

Here a reordering mechanism exists, which transmits the highest priority packets first if RETRY acknowledges. Once in the FIFO, the data is guaranteed to be transmitted through the pins. Alternatively, if an intended flow has been shut down, the peripheral signals the CPU with an interrupt to notify that the packet was not sent and sets the completion code to 010b in the status register. The registers are held until the interrupt service routine is complete before the BSY signal is released (BSY=0 in LSUn_REG6) and the CPU can then rewrite or overwrite the transfer descriptors with new data. Figure 15 illustrates the data path and buffering that is required to support the Load/Store module.

SPRUE13A –September 2006 Serial RapidIO (SRIO) 39

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