Texas Instruments TMS320TCI648x manual Lsuicsr

limiting which devices can access a mailbox		45
line rate versus PLL output clock frequency		29
LINK_STATUS field of SPn_LM_RESP 201
LINK_TIMEOUT_EN field of SPn_RATE_EN		221
LINK_TIMEOUT field of SPn_ERR_DET	219
link maintenance command field for port n	240
link-request control symbol generation register 200

link responses

acknowledge or link-response control symbol overdue at port n

rate counting enable field					222
status field		220
link-response valid field 201
link status received			201
non-outstanding ackID at port n
rate counting enable field					222
status field		220
link timeout at port n
rate counting enable field				222
status field	220
Little Endian versus Big Endian					68
Load/Store module
data flow diagram			39
data path description 39
enable bit	119
enable status bits			117, 120
power down state			43
Load/Store units. See LSUs				40
local configuration space base address CSRs									191, 192
lockout field for port n			207
logical blocks of the SRIO peripheral						71
logical layer
content in SRIO data stream					22
definition	16
logical layer buffers
in packet transmission discussion						75
in SRIO component block diagram						26
logical/transport error handling and logging								83
logical/transport layer address capture CSR									215
logical/transport layer control capture CSR								217
logical/transport layer device ID capture CSR									216
logical/transport layer error detect CSR							210
logical/transport layer error enable CSR							212

logical/transport layer high address capture CSR 214

LOG. See logical layer 23
loopback mode 113
loop bandwidth field for SERDES PLL	130
LOS field of SERDES_CFGRXn_CNTL	125

loss of signal detection in SERDES receiver 126

LSBs of address associated with logical/transport error 215

LSBs of destination ID associated with logical/transport error 216

LSBs of source ID associated with logical/transport error 216

LSU_ICCR 141

LSU_ICRR0 to LSU_ICRR3 147

SPRUE13A –September 2006

	SRIO Registers
LSU_ICSR 138
LSU congestion control flow mask register 162
LSU control register 0	155
LSU control register 1	156
LSU control register 2	157
LSU control register 3	158
LSU control register 4	159
LSU control register 5	160
LSU control register 6	161

LSU interrupt condition clear register 141 LSU interrupt condition routing registers 147

LSU interrupt condition status register			138
LSUn_FLOW_MASKS 162
LSUn_REG0	155
LSUn_REG1	156
LSUn_REG2	157
LSUn_REG3	158
LSUn_REG4	159
LSUn_REG5	160
LSUn_REG6	161
LSUs
data path description 39
enable bit	119
enable status bits 117, 120
handling of unavailable outbound credit				76
in Load/Store module data flow diagram				39
in SRIO component block diagram			26
register introduction 35
register-load timing diagram 37
register programming example 38
RX operation		42
TX operation		40

M

MAILBOX_MASK field of RXU_MAP_Ln 178
mailboxes and letters 43
mailbox field of RX buffer descriptor	47
MAILBOX field of RXU_MAP_Ln 178
mailbox field of TX buffer descriptor	52

mailbox number associated with logical/transport error 217

mailbox number masking 45

mailbox to queue mapping during message reception

introduction	44
register descriptions 177
maintenance packets
Ftypes and Ttypes		25
introduction	63
masking mailbox and letter numbers 45
master device mode field 199
MAU
enable bit	119
enable status bits		117, 120

handling of unavailable outbound credit 76 in SRIO component block diagram 26

MAX_RETRY_EN field of SPn_CTL_INDEP 236

Index 247

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