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SRIO Registers

5.15 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL)

There are four of these registers, to support four ports (see Table 63). The general form for a SERDES transmit channel configuration register is summarized by Figure 76 and Table 64. See Section 2.3.2.1 for a complete explanation of the programming of this register.

Table 63. SERDES_CFGn_CNTL Registers and the Associated Ports

Register

Address Offset

Associated Port

SERDES_CFG0_CNTL

0120h

Port 0, Port 1, Port 2, and Port 3

SERDES_CFG1_CNTL

0124h

Not Used. Program as

 

 

0x00000000

SERDES_CFG2_CNTL

0128h

Not Used. Program as

 

 

0x00000000

SERDES_CFG3_CNTL

012Ch

Not Used. Program as

 

 

0x00000000

Figure 76. SERDES Macro Configuration Register n (SERDES_CFGn_CNTL)

31

 

 

 

 

 

 

 

16

 

 

 

Reserved

 

 

 

 

 

 

 

R-0

 

 

 

 

15

10

9

8

7

6

5

1

0

Reserved

 

LB

 

Reserved

 

 

MPY

ENPLL

R-0

 

R/W-0

 

R-0

 

 

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= Value after reset

Table 64. SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) Field Descriptions

Bit

Field

Value

Description

31–10

Reserved

0

Reserved

9–8

LB

 

Loop bandwidth. Specify loop bandwidth settings. Jitter on the reference clock will

 

 

 

degrade both the transmit eye and receiver jitter tolerance thereby impairing system

 

 

 

performance. Performance of the integrated PLL can be optimized according to the

 

 

 

jitter characteristics of the reference clock via the LB field.

 

 

00b

Frequency dependent bandwidth. The PLL bandwidth is set to a twelfth of the

 

 

 

frequency of RIOCLK/RIOCLK. This setting is suitable for most systems that input the

 

 

 

reference clock via a low jitter input cell, and is required for standards compliance

 

 

01b

Reserved

 

 

10b

Low bandwidth. The PLL bandwidth is set to a twentieth of the frequency of

 

 

 

RIOCLK/RIOCLK, or 3MHz (whichever is larger). In systems where the reference

 

 

 

clock is directly input via a low jitter input cell, but is of lower quality, this setting may

 

 

 

offer better performance. It will reduce the amount of reference clock jitter transferred

 

 

 

through the PLL. However, it also increases the susceptibility to loop noise generated

 

 

 

within the PLL itself. It is difficult to predict whether the improvement in the former will

 

 

 

more than offset the degradation in the latter.

 

 

11b

High bandwidth. The PLL bandwidth is set to a eighth of the frequency of

 

 

 

RIOCLK/RIOCLK. This is the setting appropriate for systems where the reference

 

 

 

clock is cleaned through an ultra low jitter LC-based PLL. Standards compliance will

 

 

 

be achieved even if the reference clock input to the cleaner PLL is outside the

 

 

 

specification for the standard.

7–6

Reserved

0

Reserved

130

Serial RapidIO (SRIO)

SPRUE13A –September 2006

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Texas Instruments TMS320TCI648x manual Serdes Macro Configuration Register n SERDESCFGnCNTL