Texas Instruments TMS320TCI648x manual 139

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SRIO Registers

Table 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions (continued)

Bit	Field	Value	Description
19	ICS19	0	LSU3 interrupt condition not detected.
		1	LSU3 interrupt condition detected. Transaction was not sent due to unsupported transaction type or
			invalid field encoding.
18	ICS18	0	LSU3 interrupt condition not detected.
		1	LSU3 interrupt condition detected. Transaction was not sent due to Xoff condition.
17	ICS17	0	LSU3 interrupt condition not detected.
		1	LSU3 interrupt condition detected. Non-posted transaction received ERROR response, or error in
			response payload.
16	ICS16	0	LSU3 interrupt condition not detected.
		1	LSU3 interrupt condition detected. Transaction complete, No errors (posted/non-posted). Enable for
			this interrupt is ultimately controlled by the Interrupt Req bit of LSU3_REG4. This allows
			enabling/disabling on a per request basis. For optimum LSU performance, interrupt pacing should
			not be used on the LSU interrupts.
15	ICS15	0	LSU2 interrupt condition not detected.
		1	LSU2 interrupt condition detected. Packet not sent due to unavailable outbound credit at given
			priority.
14	ICS14	0	LSU2 interrupt condition not detected.
		1	LSU2 interrupt condition detected. Retry Doorbell response received or Atomic test-and-swap was
			not allowed (semaphore in use).
13	ICS13	0	LSU2 interrupt condition not detected.
		1	LSU2 interrupt condition detected. Transaction was not sent due to DMA data transfer error.
12	ICS12	0	LSU2 interrupt condition not detected.
		1	LSU2 interrupt condition detected. Transaction timeout occurred.
11	ICS11	0	LSU2 interrupt condition not detected.
		1	LSU2 interrupt condition detected. Transaction was not sent due to unsupported transaction type or
			invalid field encoding.
10	ICS10	0	LSU2 interrupt condition not detected.
		1	LSU2 interrupt condition detected. Transaction was not sent due to Xoff condition.
9	ICS9	0	LSU2 interrupt condition not detected.
		1	LSU2 interrupt condition detected. Non-posted transaction received ERROR response, or error in
			response payload.
8	ICS8	0	LSU2 interrupt condition not detected.
		1	LSU2 interrupt condition detected. Transaction complete, No errors (posted/non-posted). Enable for
			this interrupt is ultimately controlled by the Interrupt Req bit of LSU2_REG4. This allows
			enabling/disabling on a per request basis. For optimum LSU performance, interrupt pacing should
			not be used on the LSU interrupts.
7	ICS7	0	LSU1 interrupt condition not detected.
		1	LSU1 interrupt condition detected. Packet not sent due to unavailable outbound credit at given
			priority.
6	ICS6	0	LSU1 interrupt condition not detected.
		1	LSU1 interrupt condition detected. Retry Doorbell response received or Atomic test-and-swap was
			not allowed (semaphore in use).
5	ICS5	0	LSU1 interrupt condition not detected.
		1	LSU1 interrupt condition detected. Transaction was not sent due to DMA data transfer error.
4	ICS4	0	LSU1 interrupt condition not detected.
		1	LSU1 interrupt condition detected. Transaction timeout occurred.
3	ICS3	0	LSU1 interrupt condition not detected.
		1	LSU1 interrupt condition detected. Transaction was not sent due to unsupported transaction type or
			invalid field encoding.
2	ICS2	0	LSU1 interrupt condition not detected.
		1	LSU1 interrupt condition detected. Transaction was not sent due to Xoff condition.
SPRUE13A –September 2006			Serial RapidIO (SRIO)	139
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