Texas Instruments TMS320TCI648x manual Ssize

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SRIO Functional Description

	Table 21. TX Buffer Descriptor Field Definitions (continued)
Field	Description
ssize	RIO standard message payload size. Indicates how the hardware should segment the
	outgoing message by specifying the maximum number of double-words per packet. If
	the message is a multi-segment message, this field remains the same for all outgoing
	segments. All segments of the message, except for the last segment, have payloads
	equal to this size. The last message segment may be equal or less than this size.
	Maximum message size for a 16 segment message is shown below.
	Message_length/16 must be less than or equal to Ssize, if not, the message is not sent
	and CC 101b is set. Written by the DSP core.
	0000b - 1000b: Reserved
	1001b: 1 Double-word payload (Supports up to a 128-byte message)
	1010b: 2 Double-word payload (Supports up to a 256-byte message)
	1011b: 4 Double-word payload (Supports up to a 512-byte message)
	1100b: 8 Double-word payload (Supports up to a 1024-byte message)
	1101b: 16 Double-word payload (Supports up to a 2048-byte message)
	1110b: 32 Double-word payload (Supports up to a 4096-byte message)
	1111b: Reserved
mailbox	Destination Mailbox: Specifies the mailbox to which the message will be sent. Written
	by the DSP core.
	000000b: Mailbox 0
	000001b: Mailbox 1
	. . .
	000100b: Mailbox 4
	. . .
	111111b: Mailbox 63
	For multi-segment messages, only the 2 LSBs of this mailbox field are valid. Hardware
	will ignore the 4 MSBs of this field if the outgoing message is multi-segment.

Once the port controls the buffer descriptor, the DEST_ID field can be queried to determine flow control. If the transaction has been flow controlled, the DMA bus READ request is postponed so that the TX buffer space is not wasted. Because buffer descriptors cannot be reordered in the link list, if the transaction at the head of the buffer descriptor queue is flow controlled, head-of-line (HOL) blocking will occur on that queue. When this occurs, all transactions located in that queue are stalled. To counter the effects and reduce back-up of more TX packets, multiple queues are available. The peripheral supports a total of 16 assignable TX queues and their associated TX DMA state registers. The transmission order between queues is based on a programmable weighted round-robin scheme at the message level. The programmable control registers are shown in Figure 23. This scheme allows configurability of the queue transmission order, as well as the weight of each queue within the round robin.

The TX state machine begins by processing the current TX_Queue_Map(n). It will attempt to process the queue and number of buffer descriptors from that queue programmed in this mapping entry. Then it will move to TX_Queue_Map(n+1), followed by TX_Queue_Map(n+2) and so forth. It is important to note that this mapping order is fixed in a circular pattern. Each mapper can point to any queue and multiple mappers can point to a single queue. If a mapper points to an inactive queue, the peripheral recognizes this and moves to the next mapper. In order for an active queue to transmit packets, at least one mapper must be pointing to that queue. The default settings dictate an equally weighted round-robin that starts on queue0 and increments by one until reaching queue15.

The round-robin scheme does not provide precise control over the order of data sent out of the device. The ordering of the messages provided by the entries in the Weighted Round Robin Programming Registers is not an absolute guarantee of the actual transmission order or receive order of the messages. For example, take a case where there are two active queues and the TX_Queue_Map registers are setup to continuously send 2 messages from Queue 0, followed by 1 message from Queue 1. If the first message from Queue 0 attempts to reuse a mailbox/letter combination already in use (Content Addressable Memory (CAM) violation), or fails to gain outbound credit due to buffer congestion at a given priority, then the state machine will re-evaluate the TX_Queue_Map to decide on the next step. Since the

54 Serial RapidIO (SRIO) SPRUE13A –September 2006

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