![](/images/new-backgrounds/1192952/192952303x1.webp)
www.ti.com
SRIO Registers
Table 84. Interrupt Status Decode Register (INTDSTn_DECODE) Field Descriptions (continued)
Bit | Field | Value | Description |
15 | ISD15 | 0 | No interrupt request routed to this bit. |
|
| 1 | Interrupt request detected. Possible interrupt sources: |
|
|
| ∙ Doorbell 0, bit 15 (bit 15 of DOORBELL0_ICSR) |
|
|
| ∙ Doorbell 1, bit 15 (bit 15 of DOORBELL1_ICSR) |
|
|
| ∙ Doorbell 2, bit 15 (bit 15 of DOORBELL2_ICSR) |
|
|
| ∙ Doorbell 3, bit 15 (bit 15 of DOORBELL3_ICSR) |
14 | ISD14 | 0 | No interrupt request routed to this bit. |
|
| 1 | Interrupt request detected. Possible interrupt sources: |
|
|
| ∙ Doorbell 0, bit 14 (bit 14 of DOORBELL0_ICSR) |
|
|
| ∙ Doorbell 1, bit 14 (bit 14 of DOORBELL1_ICSR) |
|
|
| ∙ Doorbell 2, bit 14 (bit 14 of DOORBELL2_ICSR) |
|
|
| ∙ Doorbell 3, bit 14 (bit 14 of DOORBELL3_ICSR) |
13 | ISD13 | 0 | No interrupt request routed to this bit. |
|
| 1 | Interrupt request detected. Possible interrupt sources: |
|
|
| ∙ Doorbell 0, bit 13 (bit 13 of DOORBELL0_ICSR) |
|
|
| ∙ Doorbell 1, bit 13 (bit 13 of DOORBELL1_ICSR) |
|
|
| ∙ Doorbell 2, bit 13 (bit 13 of DOORBELL2_ICSR) |
|
|
| ∙ Doorbell 3, bit 13 (bit 13 of DOORBELL3_ICSR) |
12 | ISD12 | 0 | No interrupt request routed to this bit. |
|
| 1 | Interrupt request detected. Possible interrupt sources: |
|
|
| ∙ Doorbell 0, bit 12 (bit 12 of DOORBELL0_ICSR) |
|
|
| ∙ Doorbell 1, bit 12 (bit 12 of DOORBELL1_ICSR) |
|
|
| ∙ Doorbell 2, bit 12 (bit 12 of DOORBELL2_ICSR) |
|
|
| ∙ Doorbell 3, bit 12 (bit 12 of DOORBELL3_ICSR) |
11 | ISD11 | 0 | No interrupt request routed to this bit. |
|
| 1 | Interrupt request detected. Possible interrupt sources: |
|
|
| ∙ Doorbell 0, bit 11 (bit 11 of DOORBELL0_ICSR) |
|
|
| ∙ Doorbell 1, bit 11 (bit 11 of DOORBELL1_ICSR) |
|
|
| ∙ Doorbell 2, bit 11 (bit 11 of DOORBELL2_ICSR) |
|
|
| ∙ Doorbell 3, bit 11 (bit 11 of DOORBELL3_ICSR) |
10 | ISD10 | 0 | No interrupt request routed to this bit. |
|
| 1 | Interrupt request detected. Possible interrupt sources: |
|
|
| ∙ Doorbell 0, bit 10 (bit 10 of DOORBELL0_ICSR) |
|
|
| ∙ Doorbell 1, bit 10 (bit 10 of DOORBELL1_ICSR) |
|
|
| ∙ Doorbell 2, bit 10 (bit 10 of DOORBELL2_ICSR) |
|
|
| ∙ Doorbell 3, bit 10 (bit 10 of DOORBELL3_ICSR) |
9 | ISD9 | 0 | No interrupt request routed to this bit. |
|
| 1 | Interrupt request detected. Possible interrupt sources: |
|
|
| ∙ Doorbell 0, bit 9 (bit 9 of DOORBELL0_ICSR) |
|
|
| ∙ Doorbell 1, bit 9 (bit 9 of DOORBELL1_ICSR) |
|
|
| ∙ Doorbell 2, bit 9 (bit 9 of DOORBELL2_ICSR) |
|
|
| ∙ Doorbell 3, bit 9 (bit 9 of DOORBELL3_ICSR) |
8 | ISD8 | 0 | No interrupt request routed to this bit. |
|
| 1 | Interrupt request detected. Possible interrupt sources: |
|
|
| ∙ Doorbell 0, bit 8 (bit 8 of DOORBELL0_ICSR) |
∙ Doorbell 1, bit 8 | (bit 8 of DOORBELL1_ICSR) | |
∙ | Doorbell 2, bit 8 | (bit 8 of DOORBELL2_ICSR) |
∙ | Doorbell 3, bit 8 | (bit 8 of DOORBELL3_ICSR) |
152 | Serial RapidIO (SRIO) | SPRUE13A |