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TMS320TCI648x
manual
Users Guide
Models:
TMS320TCI648x
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256 pages
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Component Block Diagram
Outputerrorenc
Spipdiscoverytimer
Control Symbols
Maintenance
Serdes Configuration Example
Reset and Power Down State
Rxiodmaaccess
Command
Srio Pins
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TMS320TCI648x Serial RapidIO (SRIO)
User's Guide
Literature Number: SPRUE13A
September 2006
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Contents
Users Guide
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Contents
Errrstevnticsr
Port Link Maintenance Request CSR n SP n Lmreq
List of Figures
INTDSTnRATECNTL Interrupt Rate Control Register
Transmit Cppi Supported Flow Mask Registers
Port-Write-In Capture CSRs
List of Tables
PF16BCNTL Registers
LSUnREG6 Registers and the Associated LSUs
SP n Errdet Registers and the Associated Ports
Read This First
Trademarks
RapidIO Architectural Hierarchy
General RapidIO System
Overview
RapidIO Interconnect Architecture
Physical Layer 1x/4x LP-Serial Specification
Features Supported in Srio Peripheral
RapidIO Feature Support in Srio
Standards External Devices Requirements
Features Not Supported
TI Devices Supported By This Document
TI Devices Supported By This Document
Peripheral Data Flow
Overview
Registers Checked for Multicast DeviceID
Registers Checked For Multicast DeviceID
Operation Sequence
Srio Packets
Example Packet Streaming Write
Operation Sequence
4x RapidIO Packet Data Stream Streaming-Write Class
Control Symbols
Srio Packet Type
Srio Pins
Packet Types
Ftype Ttype Packet Type
Functional Operation
Component Block Diagram
Pin Description
Srio Component Block Diagram
Enabling the PLL
Serdes Macro and its Configurations
MPY Enpll
MPY
Bit Field Value Description
Effect of the Rate Bits
Line Rate versus PLL Output Clock Frequency
Frequency Range versus MPY Value
Enabling the Receiver
LOS Align Term Invpair Rate Buswidth Enrx
CDR
Bit Field
LOS
Enabling the Transmitter
EQ Bits
CFGRX22-19
Swing
DE Bits of SERDESCFGTXnCNTL
Amplitude Reduction
DE Bits
Swing Bits of SERDESCFGTXnCNTL
Serdes Configuration Example
Direct I/O Operation
Swing Bits
LSU Register Field RapidIO Packet Header Field
LSU Control/Command Register Fields
LSU Register Field Function
LSU Status Register Fields
BSY
LSU Registers Timing
Detailed Data Path Description
Example Burst Nwriter
Write Transactions
Direct I/O TX Operation
Read Transactions
Direct I/O RX Operation
Segmentation
Message Passing
Reset and Power Down State
Cppi RX Scheme for RapidIO
RX Operation
Message Request Packet
Mailbox to Queue Mapping Register L n Rxumapl n
RX DMA State Completion Pointer CP Address Offset 680h-6BCh
Mailbox to Queue Mapping Register H n Rxumaph n
Bit Name Description
Field Description
RX Buffer Descriptor Field Descriptions
DSP core uses this bit to reclaim buffers
RX Cppi Mode Explanation
Srio Functional Description
TX Operation
Cppi Boundary Diagram
TX Buffer Descriptor Field Definitions
TX DMA State Completion Pointer CP Address Offset 58h-5BCh
Field Description
TX Buffer Descriptor Field Definitions
Ssize
Srio Functional Description
TXQUEUECNTL1 Address Offset 7E4h
TXQUEUECNTL0 Address Offset 7E0h
TXQUEUECNTL2 Address Offset 7E8h
TXQUEUECNTL3 Address Offset 7ECh
TXQUEUECNTL17-4
TXQUEUECNTL13-0
TXQUEUECNTL111-8
TXQUEUECNTL23-0
TXQUEUECNTL37-4
TXQUEUECNTL33-0
TXQUEUECNTL311-8
Reset and Power Down State
RX Operation
Message Passing Software Requirements
TX Operation
Queue Mapping
Initialization Example
RX Buffer Descriptor
TX Buffer Descriptor
RX Buffer Descriptors
Start Message Passing
Maintenance
Doorbell Operation
Info Field Segments
Examples of Doorbellinfo Designations See Figure
Reg #
Bit LSUnREG5
Congestion Control
Atomic Operations
Detailed Description
FL9 FL8 FL7 FL6 FL5 FL4 FL3 FL2 FL1 FL0
Flowcntlid
FL9
Endianness
Endian Conversion TMS320TCI6482
Translation for MMR space
Reset Hierarchy
Reset and Power Down
Bus
Logical Block
Enable and Enable Status Registers
Reset and Power Down Summary
Global Enable and Global Enable Status Field Descriptions
Enstat
Block Enable and Block Enable Status Field Descriptions
RegisterBit Field
Valu Description e
Emulation
Software Shutdown Details
Peripheral Control Register PCR Field Descriptions
Peren Soft Free
TX Buffers, Credit, and Packet Reordering
Peripheral Control Register PCR Field Descriptions
Multiple Ports With 1x Operation
Unavailable Outbound Credit
Single Port With 1x or 4x Operation
Enabling the Srio Peripheral
Port Mode Register Settings
13.2 PLL, Ports, Device ID and Data Rate Initializations
Set Device ID Registers
Peripheral Initializations
Bootload Capability
Assert the Peren bit to enable logical layer data flow
Configuration and Operation
Read register to check portx1-4 OK bit
Device Wakeup
Bootload Data Movement
RX Multicast Support
Daisy Chain Operation and Packet Forwarding
Multicast DeviceID Operation
Enabling Multicast and Packet Forwarding
16BITDEVIDUPBOUND 16BITDEVIDLOWBOUND
Port
Outbound
8BITDEVIDUPBOUND
8BITDEVIDLOWBOUND
For the MAU or the RXU
For an LSU or the TXU
Pktrspnstimeout
Msgreqtimeout
Rxiodmaaccess
Unsolicitedrspns
General Description
CPU Interrupts
Interrupt Condition Status and Clear Registers
Doorbell Interrupt Condition Status and Clear Registers
Interrupt Condition Status and Clear Bits
Cppi Interrupt Condition Status and Clear Registers
Doorbell 2 Interrupt Condition Status and Clear Registers
LSU Interrupt Condition Status and Clear Registers
RX Cppi Interrupt Condition Status and Clear Registers
LSU4
Bit Associated LSU Interrupt Condition
LSU3
LSU2
ICS2 ICS1 ICS0
ICS11 ICS10 ICS9 ICS8
ICC11 ICC10 ICC9 ICC8
ICC2 ICC1 ICC0
Interrupt Function
Interrupt Clearing Sequence for Special Event Interrupts
1st Step Nd Step 3rd Step
Interrupt Condition Routing Options
Interrupt Condition Routing Registers
Doorbell Interrupt Condition Routing Registers
Interrupt Function St Step Nd Step Rd Step
ICR7 ICR6 ICR5 ICR4
Cppi Interrupt Condition Routing Registers
ICR3 ICR2 ICR1 ICR0
ICR15 ICR14 ICR13 ICR12
LSU Interrupt Condition Routing Registers
TX Cppi Interrupt Condition Routing Registers
ICR19 ICR18 ICR17 ICR16
ICR23 ICR22 ICR21 ICR20
ICR31 ICR30 ICR29 ICR28
ICR27 ICR26 ICR25 ICR24
ICR2 ICR1 ICR0
Interrupt Status Decode Registers
Interrupt Status Decode Register INTDSTnDECODE
Interrupt Pacing
Interrupt Generation
INTDSTnRATECNTL Interrupt Rate Control Register
Interrupt Handling
101
Serial RapidIO Srio Registers
Introduction
Offset Acronym Register Description
Offset Acronym Register Description
Serial RapidIO Srio Registers
INTDST4DECODE
INTDST3DECODE
INTDST5DECODE
INTDST6DECODE
QUEUE1TXDMAHDP
QUEUE0RXDMACP
QUEUE15RXDMAHDP
QUEUE1RXDMACP
QUEUE2RXDMACP
RXUMAPH7
RXUMAPL7
RXUMAPL8
RXUMAPH8
RXUMAPH30
RXUMAPL30
RXUMAPL31
RXUMAPH31
SP1CTL
SP0SILENCETIMER
Spipdiscoverytimer
SP1SILENCETIMER
SP2SILENCETIMER
Peripheral ID Register PID Field Descriptions
Peripheral Identification Register PID
Type
Class REV
Halts
Peripheral Control Register PCR
Peripheral Settings Control Register Persetcntl
Prescalerselect
Enable Serdes PLL
Peripheral Global Enable Register Gblen Field Descriptions
Peripheral Global Enable Register Gblen
Peripheral Global Enable Status Register Gblenstat
MMRs for the Srio peripheral
Block n Enable Registers and the Associated Blocks
Block n Enable Register BLKnEN
Block n Enable Register BLKnEN Field Descriptions
Register Address Offset Associated Block
Block n Enable Status Registers and the Associated Blocks
Block n Enable Status Register BLKnENSTAT
RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions
RapidIO DEVICEID1 Register DEVICEIDREG1
8BNODEID
16BNODEID
RapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions
RapidIO DEVICEID2 Register DEVICEIDREG2
Register Address Offset
PF16BCNTL Registers
PF8BCNTL Registers
Packet Forwarding Register n for 8-Bit Device IDs PF8BCNTLn
Register Address Offset Associated Port
SERDESCFGRXnCNTL Registers and the Associated Ports
Via a 50 pF capacitor to Vssa
127
SERDESCFGTX3CNTL
SERDESCFGTXnCNTL Registers and the Associated Ports
Swing Invpair Rate Buswidth Entx
129
SERDESCFGnCNTL Registers and the Associated Ports
Serdes Macro Configuration Register n SERDESCFGnCNTL
131
Doorbell nICSR Registers
DOORBELLn Interrupt Condition Status Register DOORBELLnICSR
Doorbell nICCR Registers
DOORBELLn Interrupt Condition Clear Register DOORBELLnICCR
RX Cppi Interrupt Status Register Rxcppiicsr
RX Cppi Interrupt Clear Register Rxcppiiccr
TX Cppi Interrupt Status Register Txcppiicsr
TX Cppi Interrupt Clear Register Txcppiiccr
ICS31
LSU Interrupt Condition Status Register Lsuicsr
139
140
LSU Interrupt Condition Clear Register Lsuiccr
31-17 Reserved These reserved bits return 0s when read
Errrstevnticcr Field Descriptions
Field Value Description
Doorbell nICRR Registers
= 0 to Eight interrupt destinations INTDST0-INTDST7
146
LSU Interrupt Condition Routing Registers LSUICRR0-LSUICRR3
LSU Interrupt Condition Routing Register Field Descriptions
= 0 to 2, 8 to 11, Interrupt destinations INTDST0-INTDST7
Destination
Interrupt Status Decode Register INTDSTnDECODE
TX buffer descriptor queue 4 bit 4 of Txcppiicsr
∙ Doorbell 0, bit 15 bit 15 of DOORBELL0ICSR
ISD2
ISD3
ISD1
Countdownvalue
INTDSTn Interrupt Rate Control Register INTDSTnRATECNTL
LSUnREG0 Registers and the Associated LSUs
LSUn Control Register 0 LSUnREG0
LSUn Control Register 0 LSUnREG0 Field Descriptions
Addressmsb
LSUn Control Register 1 LSUnREG1
For packet type 8 maintenance packet
LSUnREG1 Registers and the Associated LSUs
LSUn Control Register 1 LSUnREG1 Field Descriptions
LSUnREG2 Registers and the Associated LSUs
LSUn Control Register 2 LSUnREG2
LSUn Control Register 2 LSUnREG2 Field Descriptions
Dspaddress
LSUnREG3 Registers and the Associated LSUs
LSUn Control Register 3 LSUnREG3
LSUn Control Register 3 LSUnREG3 Field Descriptions
Bytecount
LSUnREG4 Registers and the Associated LSUs
LSUn Control Register 4 LSUnREG4
LSUn Control Register 4 LSUnREG4 Field Descriptions
LSUnREG5 Registers and the Associated LSUs
LSUn Control Register 5 LSUnREG5
LSUn Control Register 5 LSUnREG5 Field Descriptions
LSUnREG6 Registers and the Associated LSUs
LSUn Control Register 6 LSUnREG6
LSUn Control Register 6 LSUnREG6 Field Descriptions
Completioncode BSY
LSUnFLOWMASKS Registers and the Associated LSUs
LSUn Congestion Control Flow Mask Register LSUnFLOWMASKS
LSU n supports Flow 8 from table entry
Register
QUEUEnTXDMAHDP Registers
QUEUEnTXDMACP Registers
QUEUEnRXDMAHDP Registers
Rxcp
QUEUEnRXDMACP Registers
Transmit Queue Teardown Register Txqueueteardown
Txcppiflowmasks Registers and the Associated TX Queues
TX Queue n Flowmask Field Descriptions
Queue n supports Flow 12 from table entry
Receive Queue Teardown Register Rxqueueteardown
Receive Cppi Control Register Rxcppicntl Field Descriptions
Receive Cppi Control Register Rxcppicntl
TXQUEUECNTL1 Address Offset 07E4h
TXQUEUECNTL0 Address Offset 07E0h
TXQUEUECNTL2 Address Offset 07E8h
TXQUEUECNTL3 Address Offset 07ECh
Field Pair
TXQUEUECNTL211-8
Mailbox to Queue Mapping Registers RXUMAPLn and RXUMAPHn
0890h Mapper
For a single-segment message
Lettermask
For a multi-segment message
Letter
Segmentmapping
Queueid
Flowcntl n Registers
Flow Control Table Entry Register n FLOWCNTLn
Device Identity CAR Devid Field Descriptions
Device Identity CAR Devid
Deviceidentity Devicevendoridentity
Deviceidentity
Device Information CAR Devinfo Field Descriptions
Device Information CAR Devinfo
Devicerev
31-0
Assembly Identity CAR Asblyid Field Descriptions
Assembly Identity CAR Asblyid
Assyidentity Assyvendoridentity
Assyidentity
Assembly Information CAR Asblyinfo Field Descriptions
Assembly Information CAR Asblyinfo
Extendedfeaturesptr
Assyrev
Processing Element Features CAR Pefeat Field Descriptions
Processing Element Features CAR Pefeat
Source and target of an operation. All PEs shall at minimum
Source Operations CAR Srcop Field Descriptions
Source Operations CAR Srcop
Destination Operations CAR Destop Field Descriptions
Destination Operations CAR Destop
Read Write Streamwrite Writewith Datamess Doorbell
Resp Andswap Atomic
Addressing
Processing Element Logical Layer Control CSR Pellctl
Extendedaddressingcontrol
Lcsba
Local Configuration Space Base Address 0 CSR Lclcfghbar
Bit Field Value
Local Configuration Space Base Address 1 CSR Lclcfgbar
Base Device ID CSR Baseid Field Descriptions
Base Device ID CSR Baseid
Basedeviceid
Largebasedeviceid
Hostbasedeviceid
Host Base Device ID Lock CSR Hostbaseidlock
Component Tag CSR Comptag Field Descriptions
Component Tag CSR Comptag
Componenttag
Efptr
Efptr Efid
Timeoutvalue
Port Link Timeout Control CSR Spltctl Field Descriptions
Port Link Time-Out Control CSR Spltctl
Port Response Time-Out Control CSR Sprtctl
Port General Control CSR Spgenctl Field Descriptions
Port General Control CSR Spgenctl
Command
Port Link Maintenance Request CSR n SPnLMREQ
SPnLMREQ Registers and the Associated Ports
SP2LMREQ
SPnLMRESP Registers and the Associated Ports
Port Link Maintenance Response CSR n SPnLMRESP
SPnACKIDSTAT Registers and the Associated Ports
Port Local AckID Status CSR n SPnACKIDSTAT
Port Error and Status CSR n SPnERRSTAT Field Descriptions
Port Error and Status CSR n SPnERRSTAT
SPnERRSTAT Registers and the Associated Ports
Outputerrorstp
Outputerrorenc
Inputerrorenc
Inputerrorstp
Portuninitialized
Portok
SPnCTL Registers and the Associated Ports
Port Control CSR n SPnCTL
Port Control CSR n SPnCTL Field Descriptions
Outputportenable
Portdisable
Inputportenable
Errorcheckdisable
Rather than a parallel port
Error Reporting Block Header Register Errrptbh
Logical/Transport Layer Error Detect CSR Errdet
RX I/O DMA access error
Logical/Transport Layer Error Enable CSR Erren
Unsolicitedrespenable
Pktresptimeoutenable
Unsupportedtransenable
Rxcppisecurityenable
ADDRESS6332
Logical/Transport Layer High Address Capture CSR Haddrcapt
ADDRESS313
Logical/Transport Layer Address Capture CSR Addrcapt
Xamsbs
Msbdestid Destid
Logical/Transport Layer Device ID Capture CSR Idcapt
Msbsourceid Sourceid
Msbdestid
Ftype Ttype Msginfo
Logical/Transport Layer Control Capture CSR Ctrlcapt
Impspecific
Ftype
Port-Write Target Device ID CSR Pwtgtid Field Descriptions
Port-Write Target Device ID CSR Pwtgtid
Deviceidmsb
Deviceid
Port Error Detect CSR n SPnERRDET Field Descriptions
Port Error Detect CSR n SPnERRDET
SPnERRDET Registers and the Associated Ports
Delineationerror
Protocolerror
Linktimeout
Rcvdpktnotaccpt
Port Error Rate Enable CSR n SPnRATEEN Field Descriptions
Port Error Rate Enable CSR n SPnRATEEN
SPnRATEEN Registers and the Associated Ports
Delineationerroren
Protocolerroren
Linktimeouten
Pktunexpectedackiden
SPnERRATTRCAPTDBG0 Registers and the Associated Ports
Port n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0
Description Case of a control-symbol error
Port n Error Capture CSR 1 SPnERRCAPTDBG1
Case of a packet error
SPnERRCAPTDBG1 Registers and the Associated Ports
SPnERRCAPTDBG2 Registers and the Associated Ports
Port n Error Capture CSR 2 SPnERRCAPTDBG2
SPnERRCAPTDBG3 Registers and the Associated Ports
Port n Error Capture CSR 3 SPnERRCAPTDBG3
SPnERRCAPTDBG4 Registers and the Associated Ports
Port n Error Capture CSR 4 SPnERRCAPTDBG4
Port Error Rate CSR n SPnERRRATE Field Descriptions
Port Error Rate CSR n SPnERRRATE
SPnERRRATE Registers and the Associated Ports
SPnERRTHRESH Registers and the Associated Ports
Port Error Rate Threshold CSR n SPnERRTHRESH
Pwtimer
Discoverytimer
Port IP Mode CSR Spipmode Field Descriptions
Port IP Mode CSR Spipmode
Rstcs
Rsten
Pwen
Pwirq
Port IP Prescaler Register Ipprescal Field Descriptions
Port IP Prescaler Register Ipprescal
Prescale
Port-Write-In Capture CSR Field Descriptions
Port-Write-In Capture CSRs SPIPPWINCAPT0-3
Port Reset Option CSR n SPnRSTOPT Field Descriptions
Port Reset Option CSR n SPnRSTOPT
SPnRSTOPT Registers and the Associated Ports
Portid
SPnCTLINDEP Registers and the Associated Ports
Port Control Independent Register n SPnCTLINDEP
Illtransen
Senddbgpkt
Illtranserr
Maxretryen
SPnSILENCETIMER Registers and the Associated Ports
Port Silence Timer n Register SPnSILENCETIMER
Silencetimer
Multevntcs
SPnMULTEVNTCS Registers and the Associated Ports
Bit Field Value Description 31-0
SPnCSTX Registers and the Associated Ports
Port Control Symbol Transmit n Register SPnCSTX
STYPE0 PAR0 PAR1 STYPE1 CMD Csemb
STYPE0
Index
Comptag
Ctrlcapt
Devinfo
Pellctl
Haddrcapt
Lsuicsr
237
Pefeat
232
Srio Registers
Rxcppicntl Rxcppiiccr Rxcppiicrr RXCPPIICRR2 Rxcppiicsr
Broken link Degraded link Maximum retry error at port n
Txqueueteardown
Xoff Xon
Important Notice
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