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SRIO Functional Description
=0xFFFFFF00; // long
=0x40000000; // agent, master, undiscovered
=0x00600000; // enable i/o
=0x00600000; // enable i/o
=0x00600000; // enable i/o
=0x00600000; // enable i/o
=0x00000000 ; // clear
=0x00000000 ; // disable
=0x00000000 ; // clear
=0x00000000 ; // clear
=0x00000000 ; // clear
=0x00000000 ; // clear
//INIT_WAIT wait for lane initialization
Read register to check portx(1-4) OK bit
//polling SRIO_MAC's port_ok bit rdata =
while ((rdata & 0x00000002) != 0x00000002)
{
rdata =
}
if (srio4p1x_mode){
rdata =
while ((rdata & 0x00000002) != 0x00000002)
{
rdata =
}
rdata =
while ((rdata & 0x00000002) != 0x00000002)
{
rdata =
}
rdata =
while ((rdata & 0x00000002) != 0x00000002)
{
rdata =
}
}
Assert the PEREN bit to enable logical layer data flow
// peren |
2.3.14Bootload Capability
2.3.14.1Configuration and Operation
Figure 41 illustrates the system components involved in bootload operation. It is assumed that an external device will initiate the bootload data transfer and master the DMA interface. Upon reset, the following sequence of events must occur:
1.DSP is placed in SRIO boot mode by HW mode pins.
2.Host takes DSP out of reset (POR or RST). The peripheral’s state machines and registers are reset.
3.Internal boot-strap ROM configures device registers, including SERDES, and DMA. DSP executes internal ROM code to initialize SRIO.
∙Choice of 4 pin selectable configurations
∙Optionally, I2C boot can be used to configure SRIO
SPRUE13A | Serial RapidIO (SRIO) | 79 |