Texas Instruments TMS320TCI648x manual Srio Packets, Operation Sequence

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SRIO Functional Description

Figure 4. SRIO Peripheral Block Diagram

1.25￿to￿3.125￿Gbps

differential￿data

		10b	SERDES
	Clock		8b/10b	8b		skew-￿deLane	￿detection￿errorCRC	￿Generation
RX	recovery	S2P Clk	decode	clock					Capability
					FIFO
		10b							registers
RX	Clock		8b/10b	8b	FIFO
	recovery	S2P Clk	decode
	Clock	10b	8b/10b	8b
RX	recovery	S2P Clk	decode		FIFO
	Clock	10b	8b/10b	8b
RX	recovery	S2P Clk	decode		FIFO
	PLL		System						Control
		10b	8b/10b	8b				Packet
TX P2S		Clk			FIFO
			coding
				8b		￿stripingLane	￿generationCRC		registers
		10b	8b/10b
TX P2S		Clk	8b/10b	8b	FIFO
			coding
		10b	8b/10b	8b
TX P2S		Clk			FIFO
			coding						Command
		10b							and￿status
TX P2S		Clk	coding		FIFO
		Clock￿domain￿1					Clock￿domain￿2

feringBuf ￿and￿address ￿handoff￿data

DMA bus

Clock￿domain￿3

Within the physical layer, the data next goes to the 8-bit/10-bit (8b/10b) decode block. 8b/10b encoding is used by RapidIO to ensure adequate data transitions for the clock recovery circuits. Here the 20% encoding overhead is removed as the 10-bit data is decoded to the raw 8-bit data. At this point, the recovered byte clock is still being used.

The next step is clock synchronization and data alignment. These functions are handled by the FIFO and lane de-skewing blocks. In the RapidIO Interconnect Specification, a "lane" is one serial differential pair. The FIFO provides an elastic store mechanism used to hand off between the recovered clock domains and a common system clock. After the FIFO, the four lanes are synchronized in frequency and phase, whether 1X or 4X mode is being used. The FIFO is 8 words deep. The lane de-skew is only meaningful in the 4X mode, where it aligns each channel’s word boundaries, such that the resulting 32-bit word is correctly aligned.

The CRC error detection block keeps a running tally of the incoming data and computes the expected CRC value for the 1X or 4X mode. The expected value is compared against the CRC value at the end of the received packet.

After the packet reaches the logical layer, the packet fields are decoded and the payload is buffered. Depending on the type of received packet, the packet routing is handled by functional blocks which control the DMA access.

2.1.2SRIO Packets

The SRIO data stream consists of data fields pertaining to the logical layer, the transport layer, and the physical layer.

∙The logical layer consists of the header (defining the type of access) and the payload (if present).

∙The transport layer is partially dependent on the physical topology in the system, and consists of source and destination IDs for the sending and receiving devices.

∙The physical layer is dependent on the physical interface (i.e., serial versus parallel RapidIO) and includes priority, acknowledgment, and error checking fields.

2.1.2.1Operation Sequence

SRIO transactions are based on request and response packets. Packets are the communication element between endpoint devices in the system. A master or initiator generates a request packet which is transmitted to a target. The target then generates a response packet back to the initiator to complete the transaction.

22 Serial RapidIO (SRIO) SPRUE13A –September 2006

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