Texas Instruments TMS320TCI648x manual Flowcntlid, FL9 FL8 FL7 FL6 FL5 FL4 FL3 FL2 FL1 FL0

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SRIO Functional Description

Table 24. Flow Control Table Entry Register n (FLOW_CNTLn) Field Descriptions

Bit	Field	Value	Description
31–18	Reserved	0	These read-only bits return 0s when read.
17–16	TT		Transfer type for flow n
		00b	8-bit destination IDs
		01b	16-bit destination IDs
		1xb	Reserved
15–0	FLOW_CNTL_ID	0000h–FFFFh	Destination ID for flow n. When 8-bit destination IDs are used (TT = 00b),
			the 8 MSBs of this field are don'tcare bits.

Each transmit source, including any LSU and any TX CPPI queue, indicates which of the 16 flows it uses with a 16-bit flow mask. Figure 28 illustrates the registers that contain the flow masks, and Figure 29 illustrates the general form of an individual flow mask. As can be seen from Table 25, bits 0 through 15 of the flow mask correspond to flows 0 through 15, respectively.

The CPU must configure the flow masks upon reset. The default setting is all 1s, indicating that the transmit source supports all flows. If the register is set to all 0s, the transmit source does not support any flow, and consequently, that source is never flow-controlled. If any of the table entry counters that a transmit source supports have a corresponding non-zero Xoff count, the transmit source is flow-controlled. A simple 16-bit bus indicates the Xoff state of all 16 flows and is compared to the transmit source mask register. Each source interprets this result and performs flow control accordingly. For example, an LSU module that is flow-controlled can reload its registers and attempt to send a packet to another flow, while a TX CPPI queue that is flow-controlled may create HOL blocking issues on that queue.

Figure 28. Transmit Source Flow Control Masks

RIO_LSUn_FLOW_MASKS (Address￿Offsets:￿0x041C, 0x043C,￿0x045C,￿0x047C)

RIO_TX_CPPI_FLOW_MASKS0 (Address￿Offsets:￿0x0704)

RIO_TX_CPPI_FLOW_MASKS1 (Address￿Offsets:￿0x0708)

RIO_TX_CPPI_FLOW_MASKS2 (Address￿Offsets:￿0x070C)

RIO_TX_CPPI_FLOW_MASKS3 (Address￿Offsets:￿0x0710)

31-16	15-0
Reserved	LSU￿n￿Flow￿Mask
R,￿0x0000	R/W,￿0xFFFF
31-16	15-0
TX￿Queue1	TX￿Queue0
Flow￿Mask	Flow￿Mask
R/W,￿0xFFFF	R/W,￿0xFFFF
31-16	15-0
TX￿Queue3	TX￿Queue2
Flow￿Mask	Flow￿Mask
R/W,￿0xFFFF	R/W,￿0xFFFF
31-16	15-0
TX￿Queue5	TX￿Queue4
Flow￿Mask	Flow￿Mask
R/W,￿0xFFFF	R/W,￿0xFFFF
31-16	15-0
TX￿Queue7	TX￿Queue6
Flow￿Mask	Flow￿Mask
R/W,￿0xFFFF	R/W,￿0xFFFF

RIO_TX_CPPI_FLOW_MASKS4 (Address￿Offsets:￿0x0714)

RIO_TX_CPPI_FLOW_MASKS5 (Address￿Offsets:￿0x0718)

RIO_TX_CPPI_FLOW_MASKS6 (Address￿Offsets:￿0x071C)

RIO_TX_CPPI_FLOW_MASKS7 (Address￿Offsets:￿0x0720)

31-16	15-0
TX￿Queue9	TX￿Queue8
Flow￿Mask	Flow￿Mask
R/W,￿0xFFFF	R/W,￿0xFFFF
31-16	15-0
TX￿Queue11	TX￿Queue10
Flow￿Mask	Flow￿Mask
R/W,￿0xFFFF	R/W,￿0xFFFF
31-16	15-0
TX￿Queue13	TX￿Queue12
Flow￿Mask	Flow￿Mask
R/W,￿0xFFFF	R/W,￿0xFFFF
31-16	15-0
TX￿Queue15	TX￿Queue14
Flow￿Mask	Flow￿Mask
R/W,￿0xFFFF	R/W,￿0xFFFF

LEGEND: R/W = Read/Write; R = Read only; -n= Value after reset

Figure 29. Fields Within Each Flow Mask

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FL15

FL14

FL13

FL12

FL11

FL10

FL9

FL8

FL7

FL6

FL5

FL4

FL3

FL2

FL1

FL0

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

LEGEND: R/W = Read/Write; -n= Value after reset

SPRUE13A –September 2006	Serial RapidIO (SRIO)	67
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