Texas Instruments TMS320DM36X manual Cmpudat, Setdiv, Chsel

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Registers

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3.4CMPUDAT

The comparison A/D Upper data (CMPUDAT) register is shown in Figure 5 and described in Table 5.

Figure 5. Comparison A/D Upper Data (CMPUDAT) Register

31

10

9

0

Reserved

 

 

CMPUDAT

R-0

 

 

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 5. Comparison A/D Upper Data (CMPUDAT) Field Descriptions

Bit

Field

Value

Description

31-10

Reserved

0

Any writes to these bit(s) must always have a value of 0.

9-0

CMPUDAT

 

Comparativer data (upper) value of CMPUDAT should be the same as or larger than that of

 

 

 

CMPLDAT.

3.5SETDIV

The SETUP divide value for start A/D conversion (SETDIV) register is shown in Figure 6 and described in Table 6.

A/D conversion time is obtained by Analog switch setup time + ADC setup time + A/D conversion time. Analog switch setup time = Peripheral CLK period * (SET_DIV[5:0] + 3)*2

ADC setup time = Peripheral CLK period * (SET_DIV[15:0] + 1)*2 A/D conversion time = Peripheral CLK period* (SET_DIV[5:0] + 1)*24.

Note: A/D conversion time can't be less than 6us.

 

 

Figure 6. Setup Divide Value for Start A/D (SETDIV) Register

31

 

 

16

 

 

 

Reserved

 

 

 

R-0

15

 

 

0

 

 

 

SETDIV

 

 

 

R/W-0xFFFF

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

Table 6. Setup Divide Value for Start A/D (SETDIV) Field Descriptions

Bit

Field

Value

Description

31-16

Reserved

0

Any writes to these bit(s) must always have a value of 0.

15-0

SETDIV

 

SETDIV bits set the Analog switch setup time, ADC setup (Idle) time and A/D conversion time.

 

 

 

Analog switch setup time = Peripheral CLK period * (SET_DIV[5:0] + 3)*2

 

 

 

ADC setup time = Peripheral CLK period * (SET_DIV[15:0] + 1)*2

 

 

 

A/D conversion time = Peripheral CLK period* (SET_DIV[5:0] + 1)*24.

3.6CHSEL

The analog Input channel select (CHSEL) register is shown in Figure 7 and described in Table 8. CHSEL setting for the selection of different channel is shown in Table 7. In order to select two or more channels, ORing of these setting is needed.

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Analog to Digital Converter (ADC) Interface

SPRUFI7–March 2009

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Block Diagram ADC if Block DiagramIndustry Compliance Statement Signal DescriptionsOne-Shot Mode Operation Clock ControlReset Considerations Interrupt SupportEmulation Considerations Power ManagementEdma Event Support ADC interface Memory Map RegistersAdctl ADC Control Adctl Field DescriptionsComparator Target Channel Cmptgt Field Descriptions CmptgtCmpldat Comparison A/D Lower Data Cmpldat Field DescriptionsSetdiv Setup Divide Value for Start A/D Setdiv Field DescriptionsCmpudat ChselAD1DAT Chsel setting for Channel selectionAD0DAT Analog Input Channel Select Chsel Field Descriptions11 AD4DAT AD2DAT10 AD3DAT D Conversion Data 2 AD2DAT Field DescriptionsD Conversion Data 4 AD4DAT Field Descriptions 12 AD5DATEmuctrl D Conversion Data 5 AD5DAT Field DescriptionsImportant Notice
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