Sharp XL-3000V service manual IC802 VHiTC9462F/-1 Servo/Signal Control TC9462F 3/3

XL-3000V

IC802 VHiTC9462F/-1: Servo/Signal Control (TC9462F) (3/3)

Pin No.	Port Name	Input/Output	Function
83	DVDD	Input	D/A converting section power terminal.
84	DVR	Input	Reference voltage terminal.
85*	LO	Output	L channel data forward rotation output terminal.
86	DVSL	Input	L channel D/A converting section power terminal.
87*	TEST1	Input	Test mode terminal. To be opened usually.
88*	TEST2	Input	Test mode terminal. To be opened usually.
89*	TEST3	Input	Test mode terminal. To be opened usually.
90-93	BUS0-BUS3	Input/Output	Microcomputer interface data input/output terminal.
94	VDD	Input	Digital + power terminal.
95	VSS	—	Digital ground terminal.
96	BUCK	Input	Microcomputer interface clock input terminal.
97	/CCE	Input	Microcomputer interface chip enable signal input terminal. "L": BUS0 to 3 is active.
98*	TEST4	Input	Test mode terminal. To be opened usually.
99*	/TSMOD	Input	Local test mode selection terminal.
100	/RST	Input	Reset signal input terminal. "L": Reset.

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

IC802 VHiTC9462F/-1: Servo/Signal Control (TC9462F)

30 TMAX	29 TMAXS	28 PDO
LPFN 31
LPFO 32
PVREF 33
VCOREF 34
VCOF 35
AVSS 36
SLCO 37
RFI 38
AVDD 39
RFCT 40
RFZI 41
RFRP 42
FEI 43
SBAD 44
TSIN 45
TEI 46
TEZI 47
FOO 48
TRO 49
VREF 50
51	52	53
RFGC	TEBC	FMO

ZDET

HSSW

P2VREF

TESIO0

VDD

MONIT

COFS

SPDA

SPCK

SBSY

SFSY

DATA

VSS

VDD

CLCK

SBOK

IPF

MBOV

DOUT

AOUT

BCK

VSS

LRCK

EMPH

/UHSO

/HSO

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

PLL

TMAX

Sub-code

Digital

Status

Audio output

demodulation

out

circuit

circuit

VCO

Synchronizing RAM

EFMdemodulation

Microcomputer interface

Address

slicer

guarantee

16KRAM

Data

CLV

signal

Correction

servo

circuit

A/D

Digital equalizer

circuit

adjustment circuit

ROM

Clock

generator

1Bit

LPF

Servo control

D/A

PWM

DAC

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

FVO

DMO

2VREF

SEL

FLGA

FLGB

FLGC

FLGD

VDD

VSS

IO0

IO1

IO2

IO3

/DMOUT

/CKSE

/DACT

TESIN

TESIO1

VSS

PXI

PXO

VDD

XVSS

XI

XO

XVDD 801 TEST0 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

/RST

/TSMOD

TEST4

/CCE

BUCK

VSS

VDD

BUS3

BUS2

BUS1

BUS0

TEST3

TEST2

TEST1

DVSL

LO

DVR

DVDD

RO

DVSR

Figure 55 BLOCK DIAGRAM OF IC

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