Sharp XL-3000V service manual IC14V VHiES3883F/-1 Video CD Encoder ES3883F 1/2

XL-3000V

IC14V VHiES3883F/-1: Video CD Encoder (ES3883F) (1/2)

Pin No.	Terminal Name	Input/Output			Function
1	VSS	Input	Ground.
2*-4*	NC	—	No connect. Do not connect to these pins.
5	VCC	Input	Voltage supply, 5V.
6	DSC_CLK	Input	Clock for programming to access internal registers.
7	AUX0	Input/Output	Servo Forward Control pin.
8	DSC_D0	Input/Output	Data for programming to access internal registers.
9	AUX1	Input/Output	Servo Reverse Control pin.
10	DSC_STB	Input	Strobe for programming to access internal registers.
11	AUX2	Input/Output	Servo LDON or Control pin.
12*	DCLK/EXT_CLK	Output	Dual-purpose pin. DCLK is the MPEG decoder clock.
		Input	EXT_CLK is the extemal clock. EXT_CLK is an input during bypass PLL mode.
13	RESET_B	Input	Video reset (active low).
14	AUX07	Input/Output	Servo BRKM/Sense or Control pin/VFD_DI.
15*	MUTE	Output	Audio mute.
16	VCC	Input	Voltage supply, 5V.
17	MCLK	Input	Audio master clock.
18	AUX8	Input/Output	Servo Mute/Open or Control pin/VFD_CLK.
19	TWS/SPLL_OUT	Input	Dual-purpose pin. TWS is the transmit audio frame sync.
		Output	SPLL_OUT is the select PLL output.
20*	AUX09	Input/Output	Servo SQS0 or Control pin.
21	TSD	Input	Transmit audio data input.
22	TBCK	Input	Transmit audio bit clock.
23	RWS/SEL_PLL1	Output	Dual-purpose pin. RWS is the receive audio frame sync.
23	RWS/SEL_PLL1	Input	Pins SEL_PLL [1:0] select the PLL clock frequency for DCLK output.
			SEL_PLL1 SEL_PLL0		DCLK
			0	0	Bypass PLL (Input Mode)
			0	1	27MHz (Output Mode)
			1	0	32.4MHz (Output Mode)
			1	1	40.5MHz (Output Mode)
24	RSTOUT_B	Output	Reset output (active low).
25, 26	VSS	Input	Ground.
27*	NC (SQCK)	—	No connect. Do not connect to these pins.
28*	NC (SQSO)	—	No connect. Do not connect to these pins.
29*, 30*	NC	—	No connect. Do not connect to these pins.
31	VSS	Input	Ground.
32	VCC	Input	Voltage supply, 5V.
33	RSD/SEL_PLL0	Output	Dual-purpose pin. RSD is the receive audio data input.
33	RSD/SEL_PLL0	Input	SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK output.
			See the table for pin number 23.
34	AUX10	Input/Output	Servo SQCK or Control pin.
35	AUX11	Input/Output	3880 IRQ or Interrupt Output or Control pin.
36*	AUX12	Input/Output	CD C2PO or Interrupt or Control pins.
37	RBCK/SER_IN	Output	Dual purpose pin. RBCK is the receive audio bit clock.
		Input	SER_IN is serial input DSC mode.
			0 = Parallel DSC mode.
			1 = Serial DSC mode.
38	AUX13	Input/Output	Serial Interrupt/CD-Mute or Control pin.
39	AUX14	Input/Output	Servo SCOR(S0S1) or Interrupt Input or Control pin.
40	AUX15	Input/Output	Interrupt Input or Control pin.
41	VSSA	Input	Audio Analog ground.
42	VCM	Input	ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25V.
			Bypass to analog ground with 47 μF electrolytic in parallel with 0.1 μF.
43	VREFP	Input	DAC and ADC maximum reference. Bypass to VCMR with 10 μF in parallel with 0.1 μF.
44	VCCAA	Input	Analog VCC, 5V.

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

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