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| FUNCTION TABLE OF IC |
IC401 | ||
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Pin No. | Port Name | Function |
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1 | DI | Serial data and clock input pin for control. |
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2 | CE | Chip enable pin. Data written into an internal latch in a timing of [H] |
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| Data transfer enabled at [H] level. |
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3 | VSS | Ground pin. |
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4 | TEST | Electronic volume control pin. To be set to the VSS potential. |
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5 | LOUT | Volume + equalizer output pin. |
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6 | LBASS2 | |
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7 | LBASS1 | |
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8 | LTRE | Capacitor connection pin comprising treble band filter. |
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9 | LIN | Volume + equalizer input pin. |
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10 | LSEL0 | Input selector output pin. |
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11 | L4 | Input signal pin. |
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12* | L3 | Input signal pin. |
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13 | L2 | Input signal pin. |
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14 | L1 | Input signal pin. |
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15* | NC | No CONNECT pin. To be open or connected to VSS. |
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16* | NC | No CONNECT pin. To be open or connected to VSS. |
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17 | R1 | Input signal pin. |
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18 | R2 | Input signal pin. |
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19* | R3 | Input signal pin. |
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20 | R4 | Input signal pin. |
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21 | RSEL0 | Input selector output pin. |
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22 | RIN | Volume + equalizer input pin. |
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23 | RTRE | Capacitor connection pin comprising treble band filter. |
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24 | RBASS1 | |
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25 | RBASS2 | |
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26 | ROUT | Volume + equalizer output pin. |
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27* | NC | No CONNECT pin. To be open or connected to VSS. |
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28 | Vref | 0.5 x VDD voltage generation block for analog ground. Capacitor of several 10μF to be connected between |
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| Vref and AWSS (VSS) as a counter measure against power ripple. |
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29 | VDD | Supply pin. |
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30 | CL | Serial data and clock input pin for control. |
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In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
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