Sharp XL-3000V service manual IC15V VHiES3880F/-1 Video CD Decoder ES3880F

XL-3000V

IC15V VHiES3880F/-1: Video CD Decoder (ES3880F)

Pin No.	Terminal Name	Input/Output	Function
1	VDD	Input	Voltage supply for 3.3V.
2	RAS#	Output	DRAM row address strobe (active low).
3	DWE#	Output	DRAM write enable (active low).
4-12	DA0-DA8	Output	DRAM multiplaxed row and column address bus.
13-28	DBUS0-DBUS15	Input/Output	DRAM data bus.
29	RESET#	Input	Ayatem reset (active low).
30	VSS	Input	Ground.
31	VDD	Input	Voltage supply for 3.3V.
32-39	YUV0-YUV7	Output	Y is luminance, UV are chrominance data bus for screen video interface.
			YUV0-YUV7 for 8-bit YUV mode.
40	VSYNC	Input/Output	Vertival sync for screen video interface, programmable for rising or falling edge.
41	HSYNC	Input/Output	Horizontal sync for screen video interface, programmable for rising or falling edge.
42*	CPUCLK	Input	RISC and system clock input. CPUCLK is used only if SEL_PLL0, SEL_PLL1=00.
43	PCLK2X	Input/Output	Pixel clock; two times the actual pixel clock for screen video interface.
44	PCLK	Input/Output	Pixel clock qualifier in for screen video interface.
45,46*-49	AUX0-AUX4	Input/Output	Auxiliary control pins (AUX0 and AUX1 are open collectors).
50	VSS	Input	Ground.
51	VDD	Input	Voltage supply for 3.3V.
52-54	AUX5-AUX7	Input/Output	Auxiliary control pins.
55-62	LD0-LD7	Input/Output	RISC interface data bus.
63*	LWR#	Output	RISC interface write enable (active low).
64	LOE#	Output	RISC interface output enable (active low).
65	LCS3#	Output	RISC interface chip enable (active low).
66,67*	LCS1#, LCS0#	Output	RISC interface chip enable (active low).
68-79	LA0-LA11	Output	RISC interface address bus.
80	VSS	Input	Ground.
81	VCC	Input	Digital supply voltage for 5V.
82-87	LA12-LA17	Output	RISC interface address bus.
88	ACLK	Input/Output	Master clock for external audio DAC (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344
			MHz and 18.432 MHz).
89	AOUT/SEL_PLL0	Output	Dual-purpose pin. AOUT is the audio interface serial data output.
		Input	Pins SEL_PLL0, SEL_PLL1 select phase-lock loop (PLL) clock frequency CPUCLK for the
			Visba:
			00 = bypass PLL.
			01 = 54 MHz PLL.
			10 = 67.5 MHz PLL.
			11 = 81 MHz PLL.
90	ATCLK	Input/Output	Audio transmit bit clock.
91	ATFS/SEL_PLL1	Output	Dual-purpose pin. ATFS is the audio interface transmit frame sync.
		Input	Pins SEL_PLL0, SEL_PLL1 select phase-lock loop (PLL) clock frequency CPUCLK for the
			Viaba.
			See the SEL_PLL0 pin above for the settings.
92	DA9/DOE#	Output	Dual purpose pin: DRAM output enable (active low)/DRAM multiplexed row column
			address bus.
93	AIN	Input	Audio interface serial data input.
94	ARCLK	Input	Audio receive bit clock.
95	ARFS	Input	Audio interface receive frame sync.
96	TDMCLK	Input	TDM interface serial clock.
97	TDMDR	Input	TDM interface serial data receive.
98	TDMFS	Input	TDM interface frame sync.
99	CAS#	Output	DRAM column address strobe bank 0 (active low).
100	VSS	Input	Ground.

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

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