Appendix B Technical Summary
Memory Decode Ranges From Processor Perspective :
Memory Range | Target | Dependency/Comments |
0000 | Main Memory | TOM registers in Host Controller |
0010 |
|
|
Memory) |
|
|
000E | FWH | Bit 7 in FWH Decode Enable |
|
| Register is set |
FEC0 | I/O APIC inside ICH2 |
|
FFC0 | FWH | Bit 0 in FWH Decode Enable |
FF80 |
| Register |
FFC8 | FWH | Bit 1 in FWH Decode Enable |
FF88 |
| Register |
FFD0 | FWH | Bit 2 in FWH Decode Enable |
FF90 |
| Register is set |
FFD8 | FWH | Bit 3 in FWH Decode Enable |
FF98 |
| Register is set |
FFE0 | FWH | Bit 4 in FWH Decode Enable |
FFA0 |
| Register is set |
FFE8 | FWH | Bit 5 in FWH Decode Enable |
FFA8 |
| Register is set |
FFF0 | FWH | Bit 6 in FWH Decode Enable |
FFB0 |
| Register is set |
FFF8 | FWH | Always Enabled. |
FFB8 |
| The top two 64K blocks of this |
|
| range can be swapped as |
|
| described in Section 6.4.1. |
FF70 | FWH | Bit 3 in FWH Decode Enable 2 |
FF30 |
| Register is set |
FF60 | FWH | Bit 2 in FWH Decode Enable 2 |
FF20 |
| Register is set |
FF50 | FWH | Bit 1 in FWH Decode Enable 2 |
FF10 |
| Register is set |
FF40 | FWH | Bit 0 in FWH Decode Enable 2 |
FF00 |
| Register is set |
Anywhere in 4GB range | D110 LAN Controller | Enable via BAR in Device |
|
| 29:Function 0 (D110 LAN |
|
| Controller) |
All Other | PCI | None |
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