Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
MAX9777/MAX9778
Detailed Description
The MAX9777/MAX9778 feature 3W BTL speaker amplifiers, 200mW headphone amplifiers, input multi- plexers, headphone sensing, and comprehensive click-
interface. The MAX9778 is controlled through five logic inputs: MUTE, SHDN, HPS_EN, GAINA/B, and IN1/2
(see the Selector Guide). The MAX9777/MAX97778 fea- ture exceptional PSRR (100dB at 1kHz), allowing these devices to operate from noisy digital supplies without the need for a linear regulator.
The speaker amplifiers use a BTL configuration. The signal path is composed of an input amplifier and an output amplifier. Resistor RIN sets the input amplifier’s gain, and resistor RF sets the output amplifier’s gain. The output of these two amplifiers serves as the input to
aslave amplifier configured as an inverting
When configured as a headphone
Input Multiplexer
Each amplifier features a 2:1 input multiplexer, allowing input selection between two stereo sources. Both multi- plexers are controlled by bit 1 in the control register (MAX9777) or by the IN1/2 pin (MAX9778). A
The input multiplexer can also be used to further expand the number of gain options available from the MAX9777/MAX9778 family. Connecting the audio source to the device through two different input resis- tors (Figure 1) increases the number of gain options from two to four. Additionally, the input multiplexer allows a speaker equalization network to be switched into the speaker signal path. This is typically useful in optimizing acoustic response from speakers with small physical dimensions.
Headphone Sense Enable
The HPS input is enabled by HPS_EN (MAX9778) or the HPS_D bit (MAX9777). HPS_D or HPS_EN determines whether the device is in automatic detection mode or
MAX9777
15kΩ MAX9778
IN_1
AUDIO |
|
INPUT | 30kΩ |
IN_2
Figure 1. Using the Input Multiplexer for Gain Setting
BIAS
These devices operate from a single 5V supply, and fea- ture an internally generated,
Table 1a. MAX9777 HPS Setting
| INPUTS |
|
| GAIN | |
|
|
| MODE | ||
HPS_D |
| SPKR/HP | |||
HPS | PATH* | ||||
BIT | BIT |
| |||
|
|
| |||
|
|
|
|
| |
0 | 0 | X | BTL | A | |
|
|
|
|
| |
0 | 1 | X | SE | B | |
|
|
|
|
| |
1 | X | 0 | BTL | A or B | |
|
|
|
|
| |
1 | X | 1 | SE | A or B | |
|
|
|
|
|
*Note:
A or
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