Maxim MAX9778, MAX9777 manual Pin Configurations, Thin QFN

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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Pin Configurations

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	GAINRA	INR2	INR1	GND	BIAS	HPS	ADD
	21	20	19	18	17	16	15
GAINRB	22						14	SHDN
PGND	23						13	PGND
OUTR+	24						12	OUTL-
PVDD	25		MAX9777				11	PVDD
OUTR-	26						10	OUTL+
PGND	27						9	PGND
	+						8
SCL	28						8	GAINLB
	1	2	3	4	5	6	7
	SDA	INT	DD	DD	INL1	INL2	GAINLA
	SDA	INT	V	V	INL1	INL2	GAINLA

THIN QFN

TOP VIEW

	GAINRA	INR2	INR1	GND	BIAS	HPS	GAINA/B
	21	20	19	18	17	16	15
GAINRB	22						14	SHDN
PGND	23						13	PGND
OUTR+	24						12	OUTL-
PVDD	25		MAX9778				11	PVDD
OUTR-	26						10	OUTL+
PGND	27						9	PGND
	+						8
IN1/2	28						8	GAINLB
	1	2	3	4	5	6	7
	MUTE	HPSEN	DD	DD	INL1	INL2	GAINLA
	MUTE	HPSEN	V	V	INL1	INL2	GAINLA
			THIN QFN

MAX9777/MAX9778

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Contents MAX9778ETI+ Part Control PIN PKG Interface Package Code MAX9777ETI+Output Amplifiers Speaker MODE, HPS = GND Parameter Symbol Conditions MIN TYP MAX UnitsDigital Inputs MUTE, SHDN, HPSEN, GAINA/B, IN1/2 Bias Voltage BiasHeadphone Sense Input HPS Timing Characteristics MAX9777 Total Harmonic Distortion Plus Noise Typical Operating CharacteristicsMAX9777/MAX9778 Entering Shutdown Speaker Mode RL = 32Ω Headphone Mode Power PIN Name Function Pin DescriptionInputs Gain Mode Hpsd SPKR/HP HPS Path BIT Headphone Sense EnableDetailed Description Input MultiplexerInputs Mode Gain Path Hpsen HPS MAX9778 HPS SettingDigital Interface Wire Serial-Interface Timing DiagramADD Connection 2C Address Early Stop ConditionAddress BIT Name Value Description RegisterRegister Address BIT Name Value DescriptionMAX9777 Control Register Format Applications Information Power Dissipation and Heat SinkingBTL Speaker Amplifiers Single-Ended Headphone AmplifierReducing Cout by Adding Rseries Component SelectionLayout and Grounding Gain SelectMAX9777 Typical Application CircuitsMAX9778 Pvdd Functional DiagramsPV DD Thin QFN Pin ConfigurationsPackage Information MAX9777/MAX9778