Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux
MAX9777/MAX9778
Write Data Format There are three registers that configure the MAX9777: the MUTE register, SHDN register, and control register. In write data mode (R/W = 0), the register address and data byte follow the device address (Figure 7).
MUTE Register The MUTE register (01hex) is a read/write register that sets the MUTE status of the device. Bit 3 (MUTEL) of the MUTE register controls the left channel; bit 4 (MUTER) controls the right channel. A
SHDN Register The SHDN register (02hex) is a read/write register that controls the
in bit 0 of the SHDN register shuts down the device; a
Control Register The control register (03hex) is a read/write register that determines the device configuration. Bit 1 (IN1/IN2) con- trols the input multiplexer, a
0.Bit 4 (SPKR/HP) selects the amplifier operating mode when HPS_D = 1. A
S | ADDRESS | WR | ACK | COMMAND |
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| ACK | P |
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S | ADDRESS | WR | ACK | COMMAND |
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| ADDRESS | WR | ACK | DATA | P | |||
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| I2C SLAVE ADDRESS. |
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| SELECTS REGISTER |
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Figure 7. Write/Read Data Format Example
Table 3. MAX9777 MUTE Register Format
REGISTER |
| 0000 0001 | ||
ADDRESS |
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BIT | NAME | VALUE |
| DESCRIPTION |
7 | X | Don’t Care |
| — |
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6 | X | Don’t Care |
| — |
5 | X | Don’t Care |
| — |
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4 | MUTER | 0* |
| Unmute right channel |
1 |
| Mute right channel | ||
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3 | MUTEL | 0* |
| Unmute left channel |
1 |
| Mute left channel | ||
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2 | X | Don’t Care |
| — |
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1 | X | Don’t Care |
| — |
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0 | X | Don’t Care |
| — |
*Default state.
Table 4. MAX9777 SHDN Register Format
REGISTER ADDRESS |
| 0000 0010 | ||
BIT | NAME | VALUE |
| DESCRIPTION |
7 | RESET | 0* |
| — |
1 |
| Reset device | ||
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6 | RESET | 0* |
| — |
1 |
| Reset device | ||
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5 | RESET | 0* |
| — |
1 |
| Reset device | ||
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4 | RESET | 0* |
| — |
1 |
| Reset device | ||
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3 | RESET | 0* |
| — |
1 |
| Reset device | ||
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2 | RESET | 0* |
| — |
1 |
| Reset device | ||
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1 | X | Don’t Care |
| — |
0 | SHDN | 0* |
| Normal operation |
1 |
| Shutdown | ||
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*Default state.
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