Maxim MAX9777 Applications Information, BTL Speaker Amplifiers, Single-Ended Headphone Amplifier

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Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

MAX9777/MAX9778

Applications Information

BTL Speaker Amplifiers

The MAX9777/MAX9778 feature speaker amplifiers designed to drive a load differentially, a configuration referred to as bridge-tied load (BTL). The BTL configu- ration (Figure 8) offers advantages over the single- ended configuration, where one side of the load is connected to ground. Driving the load differentially doubles the output voltage compared to a single- ended amplifier under similar conditions. Thus, the devices’ differential gain is twice the closed-loop gain of the input amplifier. The effective gain is given by:

AVD = 2 RF

RIN

Substituting 2 x VOUT(P-P)for VOUT(P-P)into the follow- ing equations yields four times the output power due to doubling of the output voltage:

VRMS = VOUT(PP)

2 2

POUT = VRMS2

RL

Since the differential outputs are biased at midsupply, there is no net DC voltage across the load. This elimi- nates the need for DC-blocking capacitors required for single-ended amplifiers. These capacitors can be large and expensive, consume board space, and degrade low-frequency performance.

When the MAX9777 is configured to automatically detect the presence of a headphone jack, the device defaults to gain setting A when the device is in speaker mode.

Single-Ended Headphone Amplifier

The MAX9777/MAX9778 can be configured as single- ended headphone amplifiers through software or by sensing the presence of a headphone plug (HPS). In headphone mode, the inverting output of the BTL amplifier is disabled, muting the speaker. The gain is 1/2 that of the device in speaker mode, and the output power is reduced by a factor of 4.

In headphone mode, the load must be capacitively coupled to the device, blocking the DC bias voltage from the load (see the Typical Application Circuits).

Power Dissipation and Heat Sinking

Under normal operating conditions, the MAX9777/ MAX9778 can dissipate a significant amount of power. The maximum power dissipation for each package is given in the Absolute Maximum Ratings section under Continuous Power Dissipation or can be calculated by the following equation:

TJ(MAX) TA

PDISSPKG(MAX) = θJA

where TJ(MAX) is +150°C, TA is the ambient tempera- ture, and θJA is the reciprocal of the derating factor in °C/W as specified in the Absolute Maximum Ratings section. For example, θJA of the TQFN package is +29°C/W.

The increase in power delivered by the BTL configura- tion directly results in an increase in internal power dis- sipation over the single-ended configuration. The maximum power dissipation for a given VDD and load is given by the following equation:

P= 2VDD2 DISS(MAX) π2RL

+1

VOUT(P-P)

2 x VOUT(P-P)

-1

VOUT(P-P)

Figure 8. Bridge-Tied Load Configuration

If the power dissipation for a given application exceeds the maximum allowed for a given package, either reduce VDD, increase load impedance, decrease the ambient temperature, or add heatsinking to the device. Large output, supply, and ground PC board traces improve the maximum power dissipation in the package.

Thermal-overload protection limits total power dissipa- tion in these devices. When the junction temperature exceeds +160°C, the thermal-protection circuitry dis- ables the amplifier output stage. The amplifiers are enabled once the junction temperature cools by 15°C. This results in a pulsing output under continuous ther- mal-overload conditions as the device heats and cools.

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Contents Part Control PIN PKG Interface Package Code MAX9777ETI+ MAX9778ETI+Parameter Symbol Conditions MIN TYP MAX Units Output Amplifiers Speaker MODE, HPS = GNDBias Voltage Bias Digital Inputs MUTE, SHDN, HPSEN, GAINA/B, IN1/2Headphone Sense Input HPS Timing Characteristics MAX9777 Typical Operating Characteristics Total Harmonic Distortion Plus NoiseMAX9777/MAX9778 Entering Shutdown Speaker Mode RL = 32Ω Headphone Mode Power Pin Description PIN Name FunctionDetailed Description Headphone Sense EnableInputs Gain Mode Hpsd SPKR/HP HPS Path BIT Input MultiplexerMAX9778 HPS Setting Inputs Mode Gain Path Hpsen HPSWire Serial-Interface Timing Diagram Digital InterfaceEarly Stop Condition ADD Connection 2C AddressRegister Address RegisterAddress BIT Name Value Description BIT Name Value DescriptionMAX9777 Control Register Format BTL Speaker Amplifiers Power Dissipation and Heat SinkingApplications Information Single-Ended Headphone AmplifierComponent Selection Reducing Cout by Adding RseriesGain Select Layout and GroundingTypical Application Circuits MAX9777MAX9778 Functional Diagrams PvddPV DD Pin Configurations Thin QFNPackage Information MAX9777/MAX9778