7-16. IC PIN FUNCTION DESCRIPTION
•MAIN BOARD IC100
Pin No. |
| Pin Name | I/O |
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1 |
| VSS1 | — | Ground terminal (digital system) |
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2 to 15 |
| T.P | I | Input terminal for the test (fixed at “L”) |
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16 to 21 | TST0 to TST5 | I | Input terminal for the test (fixed at “L”) |
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22 to 24 | JPE1 to JPE3 | I | External condition jump terminal | “H”: condition jump (fixed at “L”) | |||
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25 |
| VDD1 | — | Power supply terminal (+3.3V) (digital system) | |||
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26 |
| AVS3 | — | Ground terminal (for D/A converter 1) (analog system) | |||
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27 |
| AOUTL1 | O | D/A converter 1 |
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| Analog signal output for front side | ||||||
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28 |
| AVD3 | — | Power supply terminal (+3.3V) (for D/A converter 1) (analog system) | |||
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29 |
| AOUTR1 | O | D/A converter 1 |
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| Analog signal output for rear side | ||||||
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30 |
| AVD5 | — | Power supply terminal (+3.3V) (for D/A converter 1) (analog system) | |||
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31 |
| AVS5 | — | Ground terminal (for D/A converter 1) (analog system) | |||
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32 |
| AVD1 | — | Power supply terminal (+3.3V) (for | |||
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33 |
| AVS1 | — | Ground terminal (for | |||
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34 |
| LREF | O | Connected to the bus control for A/D converter (for | |||
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35 |
| LIN | I | A/D converter | |||
| Tuner and bus audio input signal | ||||||
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36 |
| AVS7 | — | Ground terminal (for D/A converter 2) (analog system) | |||
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37 |
| AVD7 | — | Power supply terminal (+3.3V) (for D/A converter 2) (analog system) | |||
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38 |
| AOUTL2 | O | D/A converter 2 | Not used (open) | ||
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39 |
| AVDX | — | Power supply terminal (+3.3V) (for master clock) (analog system) | |||
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40 |
| XTLO38 | O | System clock output terminal (16.9344 MHz) |
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41 |
| XTLI38 | I | System clock input terminal (16.9344 MHz) |
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42 |
| AVSX | — | Ground terminal (for master clock) (analog system) | |||
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43 |
| AOUTR2 | O | D/A converter 2 | Not used (open) | ||
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44 |
| AVD8 | — | Power supply terminal (+3.3V) (for D/A converter 2) (analog system) | |||
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45 |
| AVS8 | — | Ground terminal (for D/A converter 2) (analog system) | |||
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46 |
| RIN | I | A/D converter | |||
| Tuner and bus audio input signal | ||||||
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47 |
| RREF | O | Connected to the bus control for A/D converter (for | |||
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48 |
| AVS2 | — | Ground terminal (for | |||
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49 |
| AVD2 | — | Power supply terminal (+3.3V) (for | |||
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50 |
| AVS6 | — | Ground terminal (for D/A converter 3) (analog system) | |||
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51 |
| AVD6 | — | Power supply terminal (+3.3V) (for D/A converter 3) (analog system) | |||
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52 |
| AOUTL3 | O | D/A converter 3 |
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| Analog signal output for rear side | ||||||
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53 |
| AVD4 | — | Power supply terminal (+3.3V) (for D/A converter 3) (analog system) | |||
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54 |
| AOUTR3 | O | D/A converter 3 |
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| Analog signal output for front side | ||||||
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55 |
| AVS4 | — | Ground terminal (for D/A converter 3) (analog system) | |||
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56 |
| VSS2 | — | Ground terminal (digital system) |
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57 |
| XRST | I | System reset signal input from the system controller (IC600) “L”: reset | |||
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58 |
| BFOT | O | Master clock signal output terminal | Not used (open) | ||
59 |
| SCK | I | Serial data transfer clock signal input from the system controller (IC600) and liquid crystal | |||
| display drive controller (IC800) |
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