Pin No. |
| Pin Name | I/O |
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73 |
| X1A | O | Sub system clock output terminal (32.768 kHz) |
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74 |
| X0A | I | Sub system clock input terminal (32.768 kHz) |
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75 |
| DAVN | I | Data transmit completed detection signal input from the RDS decoder (IC50) “H” active | ||||||
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76 |
| I | CD/MD on/off control signal input terminal (fixed at “L” in this set) | |||||||
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77 |
| I | Battery detection signal input from the SONY bus interface (IC500) and battery detect circuit | |||||||
| “L” is input at low voltage |
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78 |
| DSPREADY | I | Transfer enable signal input from the CXD2726Q (IC100) |
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| “L”: transfer prohibition , “H”: transfer permission |
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79 |
| KEYACK | I | Input of acknowledge signal for the key entry Acknowledge signal is input to accept function | ||||||
| and eject keys in the power off status | On at input of “H” |
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80 |
| AD ON |
| A/D converter power control signal output terminal |
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| O | When the KEYACK (pin ul) that controls reference voltage power for key A/D conversion input | ||||||||
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| is active, “L” is output from this terminal to enable the input |
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81 |
| ACCIN | I | Accessory detection signal input terminal | “L”: accessory on |
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82 |
| FLASH ON | O | Power on/off control signal output of the illumination LED and liquid crystal display driver | ||||||
| (IC800) | “H”: power on |
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83 |
| O | Main system power supply on/off control signal output terminal | “H”: power on | ||||||
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84 |
| TESTIN | I | Setting terminal for the test mode | “L”: test mode, Normally: fixed at “H” | |||||
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85 |
| RAMBU | I | Internal RAM reset detection signal input from the RAM reset (IC570) | ||||||
| Input terminal to check that RAM data are not destroyed due to low voltage | |||||||||
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| This checking is made within 100 msec after reset |
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86 |
| HSTX | I | Hardware standby input terminal | “L”: hardware standby mode | Reset signal input in this set | ||||
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87 |
| MD2 | I | Setting terminal for the CPU operational mode (fixed at “L” in this set) | ||||||
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88 |
| MD1 | I | Setting terminal for the CPU operational mode (fixed at “H” in this set) | ||||||
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89 |
| MD0 | I | Setting terminal for the CPU operational mode (fixed at “H” in this set) | ||||||
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90 |
| RESET | I | System reset signal input from the reset signal generator (IC560) and reset switch (S500) | ||||||
| “L”: reset | “L” is input for several 100 msec after power on, then it changes to “H” | ||||||||
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91 |
| VSS | — | Ground terminal |
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92 |
| X0 | I | Main system clock input terminal (3.68 MHz) |
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93 |
| X1 | O | Main system clock output terminal (3.68 MHz) |
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94 |
| VCC | — | Power supply terminal (+5V) |
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95 |
| ILLIN | I | Auto dimmer control illumination line detection signal input terminal | ||||||
| “L” is input at dimmer detection |
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96 |
| TELATT | I | Telephone detection signal input terminal | At input of “H”, the signal is attenuated by | |||||
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97 |
| EMPH | I | Emphasis control signal input terminal | Not used (open) |
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98 |
| F CH | O | Frequency changing terminal “H”: frequency change Not used (open) | ||||||
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99 to 102 |
| NC | O | Not used (open) |
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103 |
| 4V SEL | I | Input terminal of whether line driver is mounted or not is detected |
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| “L”: line driver is not mounted, “H”: line driver is mounted |
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104 |
| COL SEL | I | Setting terminal for the illumination color |
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| “L”: 2 color |
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105 |
| AMPATT | O | Power amplifier muting on/off control signal output terminal “H”: muting on | ||||||
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106 |
| BOOT | O | Serial data output to the liquid crystal display drive controller (IC800) | ||||||
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107 |
| DSP GAIN | O | Not used (open) |
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108 |
| NC | O | Not used (open) |
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109 |
| XR CDMD | I | Setting terminal for the internal mechanism tape or CD/MD |
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| “L”: tape, “H”: CD/MD (fixed at “L” in this set) |
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110 |
| DSP ON | O | Power supply on/off control signal output terminal “H”: DSP on | Not used (open) | |||||
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38