
SPRA921
Multiple serial input streams (A/D converters,
DIR/SPDIF
receivers)
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | Directly  | 
  | ||
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | connected to  | 
  | ||
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | |||
  | 
  | 
  | SDRAM  | 
  | 
  | 
  | 
  | other system  | 
  | |||
  | 
  | 
  | 
  | 
  | 
  | 
  | components  | 
  | ||||
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | |||
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | EMIF  | 
  | 
  | 
  | 
  | GPIO  | 
  | |||
  | McASP  | TMS320C6713  | 
  | 
  | McASP  | 
  | ||||||
  | 
  | |||||||||||
  | port 0  | 
  | 
  | port 0  | 
  | |||||||
  | 
  | digital  | 
  | 
  | 
  | |||||||
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | |||
  | 
  | 
  | 
  | 
  | 
  | signal  | 
  | 
  | 
  | 
  | ||
  | McASP  | 
  | processor  | 
  | 
  | McASP  | 
  | |||||
  | 
  | |||||||||||
  | port 1  | 
  | 
  | 
  | 
  | 
  | 
  | port 1  | 
  | |||
  | HPI  | 
  | IIC  | 
  | IIC  | 
  | ||||||
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
  | 
Multiple serial output streams (D/A converters, DIT/SPDIF line converters)
Host
processor
ROM
Serially
controlled
interface
devices
Figure 2. Generalized High Performance Multichannel Audio System
  | 32  | 
  | C6713 digital signal processor  | |
  | 
  | L1P cache  | 
  | |
  | EMIF | L2Cache/  | 
  | |
  | 
  | direct mapped  | 
  | |
  | 
  | memory  | 
  | |
  | 
  | 4K bytes total  | 
  | |
  | McASP1  | 4 banks  | 
  | |
  | 
  | 
  | ||
  | 64K  | 
  | 
  | |
  | 
  | 
  | 
  | |
  | McASP0  | bytes  | 
  | 
  | 
  | total  | 
  | 
  | |
  | 
  | (up to  | 
  | 
  | 
  | McBSP1  | 
  | 
  | |
  | 
  | 
  | 
  | |
multiplexing  | McBSP0  | Enhanced  | C67x CPU  | 
  | 
  | 
  | |||
  | DMA | 
  | 
  | |
I2C1  | controller  | 
  | 
  | |
(16  | 
  | 
  | ||
  | 
  | 
  | ||
  | channel)  | 
  | 
  | |
Pin  | I2C0  | 
  | 
  | |
L2  | 
  | 
  | ||
  | 
  | 
  | ||
  | 
  | L1D cache   | 
  | |
  | 
  | memory  | 
  | |
  | Timer 1  | 192K  | set associative  | 
  | 
  | bytes  | 4K bytes  | 
  | |
  | 
  | 
  | ||
  | Timer 0  | 
  | 
  | 
  | 
  | 
  | 
  | Clock generator  | 
  | 
  | 
  | 
  | oscillator and PLL  | Power–  | 
  | 
  | 
  | x4 through x25  | |
  | GRO  | 
  | down  | |
  | 
  | multiplier  | ||
  | 
  | logic  | ||
  | 
  | 
  | ||
  | 32  | 
  | /1 through /32  | |
  | 
  | 
  | ||
  | 
  | dividers  | 
  | |
  | HPI  | 
  | 
  | |
  | 
  | 
  | 
  | |
Figure 3. TMS3206713 CPU and Peripheral Connectivity.
4TMS320C6713 Digital Signal Processor Optimized for High Performance Multichannel Audio Systems