SPRA921
Multiple serial input streams (A/D converters,
DIR/SPDIF
receivers)
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| connected to |
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| SDRAM |
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| other system |
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| EMIF |
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| GPIO |
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| McASP | TMS320C6713 |
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| McASP |
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| port 0 |
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| port 0 |
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| digital |
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| signal |
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| McASP |
| processor |
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| McASP |
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| port 1 |
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| port 1 |
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| HPI |
| IIC |
| IIC |
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Multiple serial output streams (D/A converters, DIT/SPDIF line converters)
Host
processor
ROM
Serially
controlled
interface
devices
Figure 2. Generalized High Performance Multichannel Audio System
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| C6713 digital signal processor | |
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| L1P cache |
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| EMIF | L2Cache/ |
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| direct mapped |
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| memory |
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| 4K bytes total |
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| McASP1 | 4 banks |
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| 64K |
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| McASP0 | bytes |
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| total |
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| McBSP1 |
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multiplexing | McBSP0 | Enhanced | C67x CPU |
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| DMA |
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I2C1 | controller |
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(16 |
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| channel) |
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Pin | I2C0 |
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L2 |
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| L1D cache |
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| memory |
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| Timer 1 | 192K | set associative |
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| bytes | 4K bytes |
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| Timer 0 |
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| Clock generator |
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| oscillator and PLL | Power– |
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| x4 through x25 | |
| GRO |
| down | |
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| multiplier | ||
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| logic | ||
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| /1 through /32 | |
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| dividers |
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| HPI |
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Figure 3. TMS3206713 CPU and Peripheral Connectivity.
4TMS320C6713 Digital Signal Processor Optimized for High Performance Multichannel Audio Systems