Advantech IPPC-9151 Series Dram Clock, Sdram Cycle Length, Bank Interleave, Memory Hole

DRAM Clock

This item allows you to control the DRAM speed.

The choices are : Host Clock, HCLK+33M.

SDRAM Cycle Length

Select CAS latency time in HCLKs of 2 or 3. The system designer already set the values. Do not change the default value unless you change specifications of the installed DRAM or the installed CPU.

Bank Interleave

Please use default setting. The choices: Disabled; 2 Bank; 4 Bank.

Memory Hole

In order to improve performance, certain space in memory is reserved for ISA cards. This memory must be mapped into the memory space below

16MB. The choices: 15M-16M; Disabled.

P2C/C2P Concurrency

This item allows you to enable/disable the PCI to CPU, CPU to PCI con- currency. The choices: Enabled; Disabled.

System BIOS Cacheable

selecting Enabled allows caching of the system BIOS ROM at F0000h- FFFFFh, resulting in better system performance.

Video RAM Cacheable

Selecting Enabled allows caching of the video memory (RAM) at A0000h to AFFFFh, resulting in better video performance. However, check your AGP manual to find out if any compatibility problem exists.

Frame Buffer size

This option allows you select memory size shared to on-chip graphics.

AGP Aperture Size

Series of options are available: 4, 8, 16, 32, 64, 128 or 256 MB. Memory mapped and graphics data structures can reside in a Graphics Aperture. This area is like a linear buffer. BIOS will automatically report the start- ing address of this buffer to the O.S. The default setting is 64 MB.

AGP– 4X Mode

This item allows you to enable AGP-4X mode. The choices are: Dis- abled, Enabled

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