Sony MZ-300 specifications Pck, Vcvss

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Pin No.	Pin name	I/O	Description

95	MD2	I/O	Data input/output to/from DRAM

96	SHOCK	O*	SHOCK/RFNG output

97	MCASB	O*	CAS signal output to DRAM (NC)

98	PCK	O	VTEC system clock signal output

99	MOEB	O*	OE signal output to DRAM (NC)

100	VCVSS	—	Ground for VTEC

* : I/O on the test mode.

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Contents 873-064-13 SpecificationsSection Servicing Note General Mechanism Deck DisassemblySection LID ASSY, UPPER, Holder AssyOptical PICK-UP Assy Main BoardSection Test Mode Setting the Test ModeHow to set the Test Mode How to set the Manual mode Manual ModeOperations when the Test Mode is set How to release the Test ModeOverall Adjustment Mode NV ResetTest Mode Electrical offset adjustment method Overall adjustment mode structureDisplay segment check mode Ver 1.1 Overall CD and MO adjustment methodMZ-E300 Overall offset adjustment Overall CD and MO adjustment itemsPin No Pin name Description Section DiagramsExplanation of IC Terminals IC601 LC89642-8B-EFseq AvssXIN LrcoVcvss PCKOpenclssw XresetRmckey SetkeySLED2RCON ClvwconSLED1RCON SLED1FCONMain Board Block DiagramsRefer to page 24 for Notes Printed Wiring Boards Main /2Location Semiconductor2121 IC B/D Schematic Diagram Main /32323 Digital MZ-E300 IC Block Diagrams IC551 SC111257FCR2 IC901 XPC18A32FCR2 Main Section Section Exploded ViewsM902 Mechanism Deck Section MT-MZE300-176Main Section Electrical Parts ListElect Chip Short Date Description of Revision Revision History

PCK