HP dc7800 Power Control, Power Button Actions, Pressed Power Button Results, System State

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Power and Signal Distribution

7.3Power Control

The generation of +3, +5, and +12 VDC is controlled digitally with the PS On signal. When the PS On signal is asserted, all DC voltages are produced. When PS On is de-asserted, only auxiliary power (+5 AUX) is generated. The +5 AUX voltage is always produced as long as the system is connected to a live AC source.

7.3.1 Power Button

The PS On signal is typically controlled through the Power Button which, when pressed and released, applies a negative (grounding) pulse to the power control logic on the system board. The resultant action of pressing the power button depends on the state and mode of the system at that time and is described as follows:

 

 

Table 7-4.

 

 

 

Power Button Actions

 

 

 

 

 

 

System State

Pressed Power Button Results In:

 

 

Off

Negative pulse, of which the falling edge results in power control logic

 

 

 

asserting PS On signal to Power Supply Assembly, which then initializes. ACPI

 

 

 

four-second counter is not active.

 

 

 

 

 

 

On, ACPI Disabled

Negative pulse, of which the falling edge causes power control logic to

 

 

 

de-assert the PS On signal. ACPI four-second counter is not active.

 

 

 

 

 

 

On, ACPI Enabled

Pressed and Released Under Four Seconds:

 

 

 

Negative pulse, of which the falling edge causes power control logic to

 

 

 

generate SMI-, set a bit in the SMI source register, set a bit for button status,

 

 

 

and start four-second counter. Software should clear the button status bit within

 

 

 

four seconds and the Suspend state is entered. If the status bit is not cleared by

 

 

 

software in four seconds PS On is de-asserted and the power supply assembly

 

 

 

shuts down (this operation is meant as a guard if the OS is hung).

 

 

 

Pressed and Held At least Four Seconds Before Release:

 

 

 

If the button is held in for at least four seconds and then released, PS On is

 

 

 

negated, de-activating the power supply.

 

 

 

 

 

 

7-6

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Technical Reference Guide

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Contents Technical Reference Guide OctoberTechnical Reference Guide Contents Input/Output Interfaces Processor/Memory SubsystemSystem Support Power and Signal Distribution Integrated Graphics SubsystemSystem Bios Error Messages and Codes IndexModel Numbering Convention About this GuideAdditional Information Sources Online ViewingIntroduction Special Notices Serial NumberNotational Conventions ValuesCommon Acronyms and Abbreviations Acronyms and Abbreviations Acronym or DescriptionCPQ CMCCmos CPUFPM EscdFifo FPUAcronyms and Abbreviations Acronym or Abbreviation DescriptionPCI-E PCAPCI PCMSimm SgramSimd SmartVesa VACVDC VGASystem Overview IntroductionFeatures 4GB 8GB Feature Difference Matrix by Form FactorSodimm Dimm Function System ArchitectureArchitectural Differences By Form Factor HP Comapq dc7800 Business PC Architecture, Block diagram Intel Processor Support Components Function ChipsetChipset Components and Functionality Support Component Functions Support ComponentsSystem Memory Component Name FunctionUniversal Serial Bus Interface Mass StorageSerial and Parallel Interfaces Network Interface ControllerIntegrated Graphics Subsystem Statistics Graphics SubsystemAudio Subsystem Integrated Graphics ControllerPower Supply Electrical Specifications SpecificationsEnvironmental Specifications Factory Configuration Parameter Operating Non-operatingPhysical Specifications Parameter Usdt SFF CMTDiskette Drive Specifications Parameter MeasurementParameter Optical Drive SpecificationsDVD/CD-RW SuperMulti CD-RW/DVD-ROM Combo LightScribe ComboHard Drive Specifications Parameter 80 GB 160 GB 250 GBSystem Overview Processor/Memory Subsystem Intel Processors Intel Processor OverviewClock Processor Changing/UpgradingSupported Processors FormMemory Subsystem Memory Socket Loading Memory UpgradingMemory Mapping and Pre-allocation Channel a Channel B Socket Socket 2 Socket 4 TotalSystem Memory Map for maximum of 8 gigabytes PCI Bus Overview PCI 2.3 Bus OperationPCI Component Configuration Access PCI Bus PCI Component Function # Device # Wired toTransaction Protocol Layer PCI Express Bus OperationSoftware/Driver Layer PCI Bus Mastering DevicesPCI Interrupts PCI Power Management SupportOption ROM Mapping Link LayerPCI 2.3 Bus Connector Pinout PCI ConnectorsPCI 2.3 Connector PCI Express Connectors PCI Express Bus Connector PinoutInterrupts Apic ModeSystem Resources ModePCI Interrupt Distribution Direct Memory AccessConnector PCI slot 1 PCI slot 2 PCI slot 3 System Interrupts System BoardReal-Time Clock and Configuration Memory Clearing CmosStandard Cmos Locations Configuration Memory Cmos MapSystem Management Security FunctionsCable Lock Provision Power-On / Setup PasswordSetup Password Interface SecurityAcpi Wake-Up Events Power ManagementSmart Cover Lock Optional Acpi Wake-Up Event System Wakes FromThermal Sensing and Cooling System Status PowerLED Beeps Action RequiredSystem Status System Operational Status LED IndicationsRegister Map and Miscellaneous Functions System I/O MapSystem I/O Map Gpio FunctionsICH9 Functions Controller Functions Input/Output Interfaces Pin Description Pin Sata Connector PinoutSata Interface Pata Interface Pin Slim IDE Connector PinoutPin Signal Diskette Drive Interface Pin Diskette Drive Connector Pinout Pin Signal DescriptionDB-9 Serial Connector Pinout Serial InterfaceExtended Capabilities Port Mode Standard Parallel Port ModeEnhanced Parallel Port Mode Parallel InterfacePin Signal Function Parallel Interface ConnectorDB-25 Parallel Connector Pinout Keyboard/Pointing Device Interface Keyboard Interface OperationPointing Device Interface Operation Keyboard/Pointing Device Interface ConnectorKeyboard/Pointing Device Connector Pinout DataController Signals USDT, SFF Form Factors CMT Form Factor USB ConnectorUSB Connector Location Universal Serial Bus InterfaceUSB Cable Length Data USB Connector PinoutUSB Cable Data USB Color CodeAudio Subsystem Functional Block Diagram Audio SubsystemAudio Multistreaming HD Audio ControllerHD Audio Link Bus ADC/DAC Audio SpecificationsHD Audio Subsystem Specifications Network Interface Controller LAN I/F NICAlert Standard Format Support Power Management SupportWake-On-LAN Support NIC Specifications NIC ConnectorNIC Specifications Parameter Compatibility standard orprotocolIntegrated Graphics Subsystem Q35 IGC, Block diagram Functional DescriptionSdram Installed Maximum Memory Allocation IGC Standard 2D Display ModesResolution Maximum Refresh Rate Analog Digital Monitor Display ModesUpgrading DB-15 Monitor Connector Pinout Monitor ConnectorsAnalog Monitor Connector Digital Monitor Connector Integrated Graphics Subsystem Power Distribution Usdt Power DistributionSFF Power Distribution Usdt 135-Watt Power Supply Unit SpecificationsSFF 240-Watt Power Supply Unit Specifications Min Range Current Max Surge Tolerance Loading RippleRange or Min Current Max Surge Tolerance Loading Ripple CMT Power DistributionCMT 365-Watt Power Supply Unit Specifications Shows the power supply cabling for CMT systems Energy Star CompliancyPower Button Actions Power ControlPower Button Pressed Power Button ResultsPower Button Actions Power LED Condition Wake Up Events Wake-On-LANState System Condition System Power StatesPower Transition OS Restart Consumption To S0 by RequiredSignal Distribution CR1 +5 VDC LEDSystem Board Component Designations Power and Signal Distribution System Bios Changeable Splash Screen ROM FlashingUpgrading Network Boot F12 Support Boot FunctionsBoot Device Order Memory Detection and ConfigurationVisual power LED Audible speaker Meaning Boot Error CodesBoot Error Codes Client Management Functions INT15 Function ModeClient Management Functions System ID and ROM Type Temperature StatusDrive Fault Prediction System ID NumbersSmbios Type DataUSB Legacy Support Management Engine FunctionsIndex NumericsIndex
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