Xilinx UG078 manual Online Document, Preface About This Guide, Meaning or Use Example

Page 6

Preface: About This Guide

R

Convention

 

Meaning or Use

Example

 

 

 

 

 

 

Variables in a syntax statement

 

 

 

for which you must supply

ngdbuild design_name

 

 

values

 

 

 

 

 

 

 

 

See the Development System

Italic font

 

References to other manuals

Reference Guide for more

 

 

 

information.

 

 

 

 

 

 

 

If a wire is drawn so that it

 

 

Emphasis in text

overlaps the pin of a symbol, the

 

 

 

two nets are not connected.

 

 

 

 

 

 

An optional entry or parameter.

 

Square brackets

[ ]

However, in bus specifications,

ngdbuild [option_name]

such as bus[7:0], they are

design_name

 

 

 

 

required.

 

 

 

 

 

Braces { }

 

A list of items from which you

lowpwr ={onoff}

 

must choose one or more

 

 

 

 

 

 

 

Vertical bar

 

Separates items in a list of

lowpwr ={onoff}

 

choices

 

 

 

 

 

 

 

Vertical ellipsis

 

 

IOB #1: Name = QOUT’

 

 

IOB #2: Name = CLKIN’

.

 

Repetitive material that has

 

.

.

 

been omitted

 

.

.

 

 

 

 

.

 

 

 

 

 

 

 

Horizontal ellipsis . . .

Repetitive material that has

allow block block_name

been omitted

loc1 loc2 ... locn;

 

 

 

 

 

 

Online Document

The following conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

 

 

See the section “Additional

Blue text

Cross-reference link to a location

Resources” for details.

in the current document

Refer to “Title Formats” in

 

 

 

Chapter 1 for details.

 

 

 

Red text

Cross-reference link to a location

See Figure 2-5in the Virtex-II

in another document

Handbook.

 

 

 

 

Blue, underlined text

Hyperlink to a website (URL)

Go to http://www.xilinx.com

for the latest speed files.

 

 

 

 

 

6

www.xilinx.com

Virtex-4 LX/SX Prototype Platform

 

 

UG078 (v1.2) May 24, 2006

Image 6
Contents Virtex-4 LX/SX Prototype Platform UG078 v1.2 May 24Revision History Date Version RevisionTable of Contents Virtex-4 LX/SX Prototype Platform Conventions Guide ContentsAdditional Resources TypographicalOnline Document Preface About This GuideMeaning or Use Example Package Contents CD-ROM ContentsIntroduction Features IntroductionVirtex-4 LX/SX Prototype Platform Block Diagram Power Switch Detailed DescriptionDetailed Description Power Supply Jacks Power Enable JumpersConfiguration Ports Serial ModeJtag Chain Jtag Termination Jumper6a. Upstream System ACE Interface Connector 6b. Downstream System ACE Interface Connector6c. Upstream Interface Connector Upstream Interface Connector 44-Pin Female6d. Downstream Interface Connector VCCO-Enable Supply JumpersPrototyping Area Oscillator Sockets Clock Name Pin NumberClock Name Differential Clock InputsSMA Clock Pin Connections for SF363 and FF668 SMA Clock Pin Connections for FF1148 and FF1513DUT Socket Pin BreakoutBreakout User LEDs Active-High FF668Program Switch Reset Switch Active-LowPlatform Flash Isprom