Xilinx UG078 manual Virtex-4 LX/SX Prototype Platform Block Diagram

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R

Introduction

Figure 1 shows a block diagram of the board.

Upstream

System ACE

Interface

Connector

Upstream

Interface

Connector

2x

LVTTL

2x Diff Pair

Clocks

SMA SMA

LEDs

VBATT

Virtex-4 DUT

Configuration

Port

To Test Points

on All Pins

PROGRAM

User RESET

Downstream
System ACE			Downstream
Interface			Interface
Connector			Connector

Power Bus and Switches

5V Jack -or- 5V Brick

LVTTL 2x

SMA SMA

2x Diff Pair Clocks

DONE INIT LED LED

VCCINT

VCC Jack

VCCO

VCCO Jack

VCCAUX VCCAUX Jack

VCC3

VCC1V8

AVCC

UG078_01_101204

Figure 1: Virtex-4 LX/SX Prototype Platform Block Diagram

Virtex-4 LX/SX Prototype Platform

www.xilinx.com

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UG078 (v1.2) May 24, 2006

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Contents UG078 v1.2 May 24 Virtex-4 LX/SX Prototype PlatformDate Version Revision Revision HistoryTable of Contents Virtex-4 LX/SX Prototype Platform Additional Resources Guide ContentsConventions TypographicalOnline Document Preface About This GuideMeaning or Use Example Package Contents CD-ROM ContentsIntroduction Introduction FeaturesVirtex-4 LX/SX Prototype Platform Block Diagram Power Switch Detailed DescriptionDetailed Description Power Enable Jumpers Power Supply JacksSerial Mode Configuration PortsJtag Termination Jumper Jtag Chain6b. Downstream System ACE Interface Connector 6a. Upstream System ACE Interface ConnectorUpstream Interface Connector 44-Pin Female 6c. Upstream Interface Connector6d. Downstream Interface Connector VCCO-Enable Supply JumpersPrototyping Area Clock Name Pin Number Oscillator SocketsSMA Clock Pin Connections for SF363 and FF668 Differential Clock InputsClock Name SMA Clock Pin Connections for FF1148 and FF1513Pin Breakout DUT SocketBreakout FF668 User LEDs Active-HighProgram Switch Reset Switch Active-LowPlatform Flash Isprom