Xilinx UG078 manual Program Switch, Reset Switch Active-Low, Platform Flash Isprom

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Detailed Description

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15. PROGRAM Switch

The active-low PROGRAM switch, when pressed, grounds the program pin on the DUT.

16. RESET Switch (Active-Low)

The RESET switch connects to a standard I/O pin on the DUT, allowing the user, after configuration, to reset the logic within the DUT. When pressed, this switch grounds the pin.

Table 11 shows the INIT pin locations for the available DUT package types.

Table 11: User Hardware and Corresponding I/O Pins

 

 

Pin Number For Package Type

 

 

 

 

 

 

 

Label

SF363

 

FF668

FF1148

FF1513

 

 

 

 

 

 

RESET

R16

 

W24

AP21

AH23

 

 

 

 

 

 

Note: Refer to the readme.txt file for implementation of this user pin.

17. DONE LED

The DONE LED indicates the status of the DONE pin on the DUT. This LED lights when DONE is high or if power is applied to the board without a part in the socket.

18. INIT LED

The INIT LED lights during initialization.

19. Platform Flash ISPROM

A32-Mb Platform Flash In-System Programmable Configuration PROM (ISPROM) is provided on the board for configuration (see Table 12). Refer to Platform Flash ISPROM (DS123) at http://direct.xilinx.com/bvdocs/publications/ds123.pdf for a detailed description.

Table 12: Platform Flash ISPROM Configuration

Label

Description

 

 

J46

Provides power to the ISPROM. These jumpers must be installed for proper

 

operation of the ISPROM.

 

 

J45

Sets the design revision control for the ISPROM.

 

 

J43

Enables or disables the ISPROM by placing the address counter in reset and

 

DATA output lines in high-impedance state.

 

 

J42

Sets the ISPROM for serial or select map configuration.

 

 

J8

Selects one of two modes of CCLK operation:

 

• ISPROM provides CCLK (PROM CLKOUT)

 

• FPGA provides CCLK (FPGA CCLK)

 

 

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Virtex-4 LX/SX Prototype Platform

 

 

UG078 (v1.2) May 24, 2006

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Contents Virtex-4 LX/SX Prototype Platform UG078 v1.2 May 24Revision History Date Version RevisionTable of Contents Virtex-4 LX/SX Prototype Platform Conventions Guide ContentsAdditional Resources TypographicalPreface About This Guide Online DocumentMeaning or Use Example CD-ROM Contents Package ContentsIntroduction Features IntroductionVirtex-4 LX/SX Prototype Platform Block Diagram Detailed Description Power SwitchDetailed Description Power Supply Jacks Power Enable JumpersConfiguration Ports Serial ModeJtag Chain Jtag Termination Jumper6a. Upstream System ACE Interface Connector 6b. Downstream System ACE Interface Connector6c. Upstream Interface Connector Upstream Interface Connector 44-Pin FemaleVCCO-Enable Supply Jumpers 6d. Downstream Interface ConnectorPrototyping Area Oscillator Sockets Clock Name Pin NumberClock Name Differential Clock InputsSMA Clock Pin Connections for SF363 and FF668 SMA Clock Pin Connections for FF1148 and FF1513DUT Socket Pin BreakoutBreakout User LEDs Active-High FF668Reset Switch Active-Low Program SwitchPlatform Flash Isprom