Cypress CY62167EV30 manuals

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Cypress CY62167EV30 Manual

14 pages501.77 Kb

CY62167EV30 MoBL
16-Mbit (1M x 16 / 2M x 8) Static RAM
- Features
- Functional Description
- Logic Block Diagram
- 2CY62167EV30 MoBL
  - Pin Configuration
    - Figure 1. 48-Ball VFBGA (6 x 7 x 1mm) / (6 x 8 x 1mm) Top View
    - Figure 2. 48-Pin TSOP I Top View
  - Product Portfolio
    - Product VCC Range (V) Speed (ns)
- 3CY62167EV30 MoBL
  - Maximum Ratings
  - Operating Range
  - Electrical Characteristics
  - Capacitance
  - 4Thermal Resistance
  - Data Retention Characteristics
  - 5Switching Characteristics
- 6CY62167EV30 MoBL
  - Document #: 38-05446 Rev. *E Page 6 of 14
  - Switching Waveforms
    - Figure 6 shows OE controlled read cycle waveforms.[20, 21] Figure 6. Read Cycle No. 2
- 7CY62167EV30 MoBL
  - Figure 7 shows WE controlled write cycle waveforms.[18, 22, 23] Figure 7. Write Cycle No. 1
  - 8Document #: 38-05446 Rev. *E Page 8 of 14
  - Figure 8 shows CE1 or CE2 controlled write cycle waveforms.[18, 22, 23] Figure 8. Write Cycle No. 2
  - t
  - Figure 9 shows WE controlled, OE LOW write cycle waveforms.[23] Figure 9. Write Cycle No. 3
  - 9Truth Table
  - 10Ordering Information
  - Package Diagrams
    - Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
  - 11Package Diagrams
    - 51-85150-*D
    - Figure 13. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183
  - 12Package Diagrams
    - 51-85183-*A
  - 13Document History Page
  - 14Sales, Solutions, and Legal Information
    - Worldwide Sales and Design Support
    - Products
    - PSoC Solutions

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