Cypress CY62167EV30 CY62167EV30 MoBL

CY62167EV30 MoBL®

Document #: 38-05446 Rev. *E Page 7 of 14

Figure 7 shows WE controlled write cycle waveforms.[18, 22, 23]

Figure 7. Write Cycle No. 1

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

NOTE 24

CE1

ADDRESS

CE2

DATA I/O

BHE/BLE

Notes

22.Data IO is high impedance if OE = VIH.

23.If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.

24.During this period the I/Os are in output state. Do not apply input signals.

[+] Feedback

Contents

Main CY62167EV30 MoBL 16-Mbit (1M x 16 / 2M x 8) Static RAM Features Functional Description Logic Block Diagram CY62167EV30 MoBL Pin Configuration Figure 1. 48-Ball VFBGA (6 x 7 x 1mm) / (6 x 8 x 1mm) Top View Figure 2. 48-Pin TSOP I Top View Product Portfolio CY62167EV30 MoBL Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance Data Retention Characteristics Switching Characteristics CY62167EV30 MoBL Document #: 38-05446 Rev. *E Page 6 of 14 Switching Waveforms Figure 6 shows OE controlled read cycle waveforms.[20, 21] Figure 6. Read Cycle No. 2 CY62167EV30 MoBL Figure 7 shows WE controlled write cycle waveforms.[18, 22, 23] Figure 7. Write Cycle No. 1 Document #: 38-05446 Rev. *E Page 8 of 14 Figure 8 shows CE1 or CE2 controlled write cycle waveforms.[18, 22, 23] Figure 8. Write Cycle No. 2 t Figure 9 shows WE controlled, OE LOW write cycle waveforms.[23] Figure 9. Write Cycle No. 3 Truth Table Ordering Information Package Diagrams Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 Package Diagrams 51-85150-*D Figure 13. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183 Package Diagrams 51-85183-*A Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions