Cypress CY7C09189V manuals
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Cypress CY7C09189V Manual
21 pages 592.52 Kb
CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAMFeatures Logic Block DiagramDocument #: 38-06043 Rev. *C Page 2 of 21 2 Functional DescriptionPin ConfigurationsDocument #: 38-06043 Rev. *C Page 3 of 21 3 Pin Configurations4 Selection GuidePin Definitions 5 Maximum RatingsOperating Range Electrical Characteristics Capacitance6 Document #: 38-06043 Rev. *C Page 6 of 21Figure 4. AC Test Loads (Applicable to -6 and -7 only) (a) Load 1 (-6 and -7 only) (b) Thvenin Eq uivalent (Load 1) (c)Three-State Delay(Load2) (a)Normal Load(Load 1) Figure 5. Load Derating Curve Figure 3. AC Test Loads (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) ALLINPUT PULSES 7 CY7C09079V/89V/99V CY7C09179V/89V/99VSwitching Characteristics 8 Document #: 38-06043 Rev. *C Page 8 of 21 CY7C09079V/89V/99V CY7C09179V/89V/99VFigure 6. Read Cycle for Flow-Through Output (FT/PIPE = VIL)[16, 17, 18, 19] 9 CY7C09079V/89V/99V CY7C09179V/89V/99VFigure 7. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[16, 17, 18, 19] Figure 8. Bank Select Pipelined Read 10 Figure 9. Left Port Write to Flow-Through Right Port Read11 Figure 10. Pipelined Read-to-Write-to-Read (OE = VIL)[19, 26, 27, 28]12 Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled)[19, 26, 27, 28]13 Figure 12. Flow-Through Read-to-Write-to-Read (OE = VIL)[17, 19, 26, 27, 28]Figure 13. Flow-Through Read-to-Write-to-Read (OE Controlled)[17, 20, 26, 27, 28] 14 Figure 14. Pipelined Read with Address Counter AdvanceFigure 15. Flow-Through Read with Address Counter Advance 15 Figure 16. Write with Address Counter Advance (Flow-Through or Pipelined Outputs)16 Figure 17. Counter Reset (Pipelined Outputs) 17 CY7C09179V/89V/99V
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