NEC PD750008 manuals
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342 pages 1.16 Mb
PD750008 USER'S MANUAL4 Major ChangesThe mark * shows major revised points. 9 CONTENTS14 LIST OF FIGURES (1/4)15 LIST OF FIGURES (2/4)16 LIST OF FIGURES (3/4)17 LIST OF FIGURES (4/4)18 LIST OF TABLES (1/2)21 CHAPTER 1 GENERAL22 21.1 FUNCTION OVERVIEW 5 CHAPTER 1 GENERAL 1.4 BLOCK DIAGRAM 25 ( )26 6Note Connect IC (VPP) to VDD, keeping the wiring as short as possible. Remark ( ) : PD75P0016. 27 7Note Connect IC (VPP) to VDD, keeping the wiring as short as possible. Remark ( ) : PD75P0016. 29 CHAPTER 2 PIN FUNCTIONS31 11CHAPTER 2 PIN FUNCTIONS Table 2-2. Non-Port Pin Functions 39 19CHAPTER 2 PIN FUNCTIONS Type F-B Type M-E*N-ch P.U.R.: Pull-Up Resistor Type E-B Type M-CV P.U.R. P.U.R.: Pull-Up Resistor P.U.R. enable P-ch IN/OUT Data Output disable Type D Figure 2-1. Pin Input/Output Circuits (2/2)P.U.R. Data Output disable P.U.R. enable V P-ch IN/OUT Type F-A Type M-D*Data Output disable Input instruction Input buffer with an intermediate withstand voltage of +13 V Note V Pull-up resistor that operates only when an input instruction is executed (valid at low voltage) N-ch (Withstand voltage:13 V) 40 202.4 CONNECTION OF UNUSED PINS Table 2-3. Connection of Unused Pins Note ( ): PD75P0016 41 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP44 24Figure 3-2. Data Memory Organization and Addressing Range of Each Addressing Mode Remark : Don't care 45 25Table 3-1. Addressing Modes 57 37Figure 3-5. General Register Configuration (4-bit Processing) 58 38Figure 3-6. General Register Configuration (8-bit Processing) 60 40Figure 3-7. PD750008 I/O Map (1/5) 61 41Figure 3-7. PD750008 I/O Map (2/5) 62 42Figure 3-7. PD750008 I/O Map (3/5) 63 43Figure 3-7. PD750008 I/O Map (4/5) Note Whether a bit can be read or written depends on the bit. 64 44Figure 3-7. PD750008 I/O Map (5/5) 65 CHAPTER 4 INTERNAL CPU FUNCTIONS69 49Figure 4-3. Program Memory Map (in PD750004) 70 50Figure 4-4. Program Memory Map (in PD750006) 71 51Figure 4-5. Program Memory Map (in PD750008) 72 52Figure 4-6. Program Memory Map (in PD75P0016) 79 59Figure 4-11. Format of Stack Pointer and Stack Bank Select Register Note PC12 and PC13 are 0 in the PD750004. PC13 is 0 in the PD750006 and PD750008. 80 60Figure 4-13. Data Restored from the Stack Memory (Mk I Mode) 81 61Figure 4-15. Data Restored from the Stack Memory (Mk II Mode) 87 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS89 69Figure 5-2. Configurations of Ports 0 and 1 90 70Figure 5-3. Configurations of Ports 2 and 7 Note For port 7 only 91 71Figure 5-4. Configurations of Ports 3n and 6n (n = 0 to 3) Note For port 6n only 92 72Figure 5-5. Configurations of Ports 4 and 5 93 73Figure 5-6. Configuration of Port 8 75 Figure 5-7. Formats of Port Mode Registers 95 Port mode register group APort mode register group B Port mode register group C98 78Table 5-2. I/O Pin Manipulation Instructions 100 80Table 5-3. Operations by I/O Port Manipulation Instructions <1> : Represents an addressing mode PORTn.bit or PORTn.@L. 104 84107 87Figure 5-12. Format of the Processor Clock Control RegisterRemarks 1. f : Output frequency from the main system clock oscillator 2. f : Output frequency from the subsystem clock oscillator 117 97 Note Caution Be sure to write a 0 in bit 2 of the CLOM. is the CPU clock selected by PCC. 120 100126 106127 107Remark ( ) for fW = 32.768 kHz 129 109Figure 5-28. Block Diagram of the Timer/Event Counter (Channel 0) 130 110 Figure 5-29. Block Diagram of the Timer Counter (Channel 1) 132 112Figure 5-30. Timer/Event Counter Mode Register (Channel 0) Format = 4.19 MHz Count pulse (CP) selection bit = 6.00 MHz 133 113Figure 5-31. Timer Counter Mode Register (Channel 1) Format = 4.19 MHz Count pulse (CP) select bit = 6.00 MHz 135 115Count pulse (CP) selection bit 136 116145 125Figure 5-39. Block Diagram of the Serial Interface 149 129Remark x: Dont care Serial clock selection bit (W) Remarks 1. Each mode can be selected using CSIE, CSIM3, and CSIM2. 181 161Figure 5-60. Operations of RELT, CMDT, RELD, and CMDD (Master) Figure 5-61. Operations of RELT, CMDT, RELD, and CMDD (Slave) 185 165Table 5-10. Various Signals Used in the SBI Mode (1/2) 186 166Table 5-10. Various Signals Used in the SBI Mode (2/2) Notes 1. When WUP = 0, IRQCSI is always set on the ninth rising edge of the SCK signal. 189 169Figure 5-67. Address Transfer Operation from Master Device to Slave Device (WUP = 1) 190 170Figure 5-68. Command Transfer Operation from Master Device to Slave Device 191 171Figure 5-69. Data Transfer Operation from Master Device to Slave Device 192 172Figure 5-70. Data Transfer Operation from Slave Device to Master Device 203 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS204 184Figure 6-1. Block Diagram of Interrupt Control Circuit*Note Noise eliminator (when the noise eliminator is selected, standby mode cannot be released.) 205 185206 <<209 189Figure 6-3. Interrupt Priority Specification Register 211 191INT4 (c) Configuration of the INT4 circuit (b) Configuration of the INT1 circuitINT4/P00 Internal bus Both-edge detection circuit Input buffer IRQ4 set signal 212 192Figure 6-5. I/O Timing of a Noise Eliminator Remark tSMP = tCY or 64/fX 213 193Figure 6-6. Format of Edge Detection Mode Registers (a) INT0 edge detection mode register (IM0) (b) INT1 edge detection mode register (IM1) 215 195223 203(1) Interrupt enable/disable Interrupt disabled INT0 and INTT0 enabled INTT0 enabled Interrupt disabled <Main program> <1> Reset <2> EI IE0 EI IET0 <3> EI <4> DI IE0 <5> DI 224 204; RBE = 0 <INT0 service program> <5> RETI Status 1 Status 0 ; RBE = 1, MBE = 0 <Main program> Reset <2> MOV Status 0 A, #1 MOV IM0, A CLR1 IRQ0 <3> EI IEBT EI IE0 EI IET0 EI <4> INT0 <1> 226 206(4) Execution of held interrupts (interrupt requests when interrupts are disabled) Reset <1> INT0 <INT0 service program> <3> INTCSI EI IE0 <INTCSI service program> EI IECSI<4> <Main program> 227 207(5) Execution of held interrupts two interrupts with lower priority occur concurrently <INTT0 service routine> RETI <1> <2> RETI Reset <INT0 service program> EI IET0 <Main program> INT0 INTT0 EI IE0 EI 229 209<1> INTCSI <5> <3> INTT0 Status 1 EI IET0 Reset <INTCSI service program> <Main program> EI IE0 EI IECSI Status 0 Status 1 <2> DI CLR1 IST0 DI IECSI DI IE4 EI <INTT0 service program> <4> RETI EI IECSI EI IE4 RETI EI IE4 EI 232 212Figure 6-10. Block Diagram of the INT2 and KR0 to KR7 Circuits 235 CHAPTER 7 STANDBY FUNCTION245 CHAPTER 8 RESET FUNCTION246 226Table 8-1. Status of the Hardware after a Reset (1/2) 247 227CHAPTER 8 RESET FUNCTION Table 8-1. Statuses of the Hardware after a Reset (2/2) 249 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM)255 CHAPTER 10 MASK OPTION257 CHAPTER 11 INSTRUCTION SET317 319 APPENDIX A FUNCTIONS OF THE PD75008, PD750008, AND PD75P0016APPENDIX B DEVELOPMENT TOOLS 321 *
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