NEC PD750004, PD750006, PD750008, PD75P0016 97, Caution Be sure to write a 0 in bit 2 of the CLOM.

97
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(3) Clock output mode register (CLOM)
The CLOM is a 4-bit register to control clock output.
The CLOM is set by a 4-bit memory manipulation instruction. No read operation is allowed on this register.
Example CPU clock F is output on the PCL/P22 pin.
SEL MB15 ; or CLR1 MBE
MOV A,#1000B
MOV CLOM,A
A RESET signal clears the CLOM to 0, disabling clock output.
Figure 5-21. Format of the Clock Output Mode Register
Caution Be sure to write a 0 in bit 2 of the CLOM.
Address
FD0H
3210
CLOM0
Symbol
CLOM
Φ output
Note
(1.05 MHz, 524 kHz, 262 kHz, 65.5 kHz)
f
X /2
3
output (524 kHz)
f
X /2
4
output (262 kHz)
0
0
1
0
0
1
11
CLOM10CLOM3
f
X /2
6
output (65.5 kHz)
(f X = 4.19 MHz)
Note Φ is the CPU clock selected by PCC.
0
1
Output disable
Output enable
Clock output enable/disable bit
Φ output
Note
(1.5 MHz, 750 kHz, 375 kHz, 93.8 kHz)
f X /2
3
output (750 kHz)
f
X /2
4
output (375 kHz)
f X /2
6
output (93.8 kHz)
Clock output frequency selection bit 
(f
X = 6.00 MHz)
0
0
1
0
0
1
11