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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Acknowledge detection flag (R)
ACKD Condition for being cleared (ACKD = 0) Condition for being set (ACKD = 1)
<1> The transfer operation is started. The acknowledge signal (ACK) is detected
<2> The RESET signal is entered. (in phase with the rising edge of SCK).
Acknowledge enable bit (R/W)
ACKE 0 Disables automatic output of the acknowledge signal. (Output by ACKT is possible.)
1 When set before transfer ACK is output in phase with the 9th clock of SCK.
When set after transfer ACK is output in phase with SCK immediately following
the set instruction execution.
Acknowledge trigger bit (W)
ACKT When set after transfer, ACK is output in phase with the next SCK. After ACK signal output,
this bit is automatically cleared to 0.
Cautions 1. Never set ACKT before or during serial transfer.
2. ACKT cannot be cleared by software.
3. Before setting ACKT, set ACKE = 0.
Command detection flag (R)
CMDD Condition for being cleared (CMDD = 0) Condition for being set (CMDD = 1)
<1> The transfer start instruction The command signal (CMD) is detected.
is executed.
<2> The bus release signal (REL)
<3> The RESET signal is entered.
<4> CSIE = 0 (Figure 5-40)
Bus release detection flag (R)
RELD Condition for being cleared (RELD = 0) Condition for being set (RELD = 1)
<1> The transfer start instruction is executed. The bus release signal (REL) is detected.
<2> The RESET signal is entered.
<3> CSIE = 0 (Figure 5-40)
<4> SVA does not match SIO when an address is
received.
Command trigger bit (W)
CMDT Control bit for command signal (CMD) trigger output. By setting CMDT = 1, the SO latch is
cleared. Then the CMDT bit is automatically cleared.
Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or
after serial transfer.