Main
PD750008
USER'S MANUAL
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Major Changes
The mark * shows major revised points.
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CONTENTS
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LIST OF FIGURES (1/4)
LIST OF FIGURES (2/4)
LIST OF FIGURES (3/4)
LIST OF FIGURES (4/4)
LIST OF TABLES (1/2)
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CHAPTER 1 GENERAL
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1.1 FUNCTION OVERVIEW
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CHAPTER 1 GENERAL 1.4 BLOCK DIAGRAM
( )
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Note Connect IC (VPP) to VDD, keeping the wiring as short as possible. Remark ( ) : PD75P0016.
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Note Connect IC (VPP) to VDD, keeping the wiring as short as possible. Remark ( ) : PD75P0016.
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CHAPTER 2 PIN FUNCTIONS
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CHAPTER 2 PIN FUNCTIONS Table 2-2. Non-Port Pin Functions
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CHAPTER 2 PIN FUNCTIONS
P-ch
Note
IN/OUT
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2.4 CONNECTION OF UNUSED PINS Table 2-3. Connection of Unused Pins
Note ( ): PD75P0016
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP
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Figure 3-2. Data Memory Organization and Addressing Range of Each Addressing Mode
Remark : Don't care
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Table 3-1. Addressing Modes
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Figure 3-5. General Register Configuration (4-bit Processing)
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Figure 3-6. General Register Configuration (8-bit Processing)
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Figure 3-7. PD750008 I/O Map (1/5)
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Figure 3-7. PD750008 I/O Map (2/5)
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Figure 3-7. PD750008 I/O Map (3/5)
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Figure 3-7. PD750008 I/O Map (4/5)
Note Whether a bit can be read or written depends on the bit.
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Figure 3-7. PD750008 I/O Map (5/5)
CHAPTER 4 INTERNAL CPU FUNCTIONS
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Figure 4-3. Program Memory Map (in PD750004)
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Figure 4-4. Program Memory Map (in PD750006)
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Figure 4-5. Program Memory Map (in PD750008)
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Figure 4-6. Program Memory Map (in PD75P0016)
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Figure 4-11. Format of Stack Pointer and Stack Bank Select Register
Note PC12 and PC13 are 0 in the PD750004. PC13 is 0 in the PD750006 and PD750008.
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Figure 4-13. Data Restored from the Stack Memory (Mk I Mode)
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Figure 4-15. Data Restored from the Stack Memory (Mk II Mode)
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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
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Figure 5-2. Configurations of Ports 0 and 1
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Figure 5-3. Configurations of Ports 2 and 7
Note For port 7 only
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Figure 5-4. Configurations of Ports 3n and 6n (n = 0 to 3)
Internal bus
Note For port 6n only
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Figure 5-5. Configurations of Ports 4 and 5
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Figure 5-6. Configuration of Port 8
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Figure 5-7. Formats of Port Mode Registers
Port mode register group A
Port mode register group B
Port mode register group C
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Table 5-2. I/O Pin Manipulation Instructions
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Table 5-3. Operations by I/O Port Manipulation Instructions
<1> : Represents an addressing mode PORTn.bit or PORTn.@L.
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Figure 5-12. Format of the Processor Clock Control Register
Remarks 1. f
: Output frequency from the main system clock oscillator 2. f
: Output frequency from the subsystem clock oscillator
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Note
Caution Be sure to write a 0 in bit 2 of the CLOM.
is the CPU clock selected by PCC.
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Remark ( ) for fW = 32.768 kHz
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TOUT0
Figure 5-28. Block Diagram of the Timer/Event Counter (Channel 0)
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Figure 5-29. Block Diagram of the Timer Counter (Channel 1)
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Figure 5-30. Timer/Event Counter Mode Register (Channel 0) Format
= 4.19 MHz
Count pulse (CP) selection bit
= 6.00 MHz
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Figure 5-31. Timer Counter Mode Register (Channel 1) Format
= 4.19 MHz
Count pulse (CP) select bit
= 6.00 MHz
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Count pulse (CP) selection bit
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Figure 5-39. Block Diagram of the Serial Interface
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Remark x: Dont care Serial clock selection bit (W)
Remarks 1. Each mode can be selected using CSIE, CSIM3, and CSIM2.
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Figure 5-60. Operations of RELT, CMDT, RELD, and CMDD (Master)
Figure 5-61. Operations of RELT, CMDT, RELD, and CMDD (Slave)
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Table 5-10. Various Signals Used in the SBI Mode (1/2)
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Table 5-10. Various Signals Used in the SBI Mode (2/2)
Notes 1. When WUP = 0, IRQCSI is always set on the ninth rising edge of the SCK signal.
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Figure 5-67. Address Transfer Operation from Master Device to Slave Device (WUP = 1)
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Figure 5-68. Command Transfer Operation from Master Device to Slave Device
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Figure 5-69. Data Transfer Operation from Master Device to Slave Device
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Figure 5-70. Data Transfer Operation from Slave Device to Master Device
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CHAPTER 6 INTERRUPT AND TEST FUNCTIONS
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Figure 6-1. Block Diagram of Interrupt Control Circuit*
Note Noise eliminator (when the noise eliminator is selected, standby mode cannot be released.)
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<
<
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Figure 6-3. Interrupt Priority Specification Register
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INT4
(c) Configuration of the INT4 circuit
(b) Configuration of the INT1 circuit
INT4/P00
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Figure 6-5. I/O Timing of a Noise Eliminator
Remark tSMP = tCY or 64/fX
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Figure 6-6. Format of Edge Detection Mode Registers (a) INT0 edge detection mode register (IM0)
(b) INT1 edge detection mode register (IM1)
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(1) Interrupt enable/disable
Interrupt disabled
INT0 and INTT0 enabled INTT0 enabled Interrupt disabled
<Main program> <1> Reset <2> EI IE0 EI IET0 <3> EI <4> DI IE0 <5> DI
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; RBE = 0
<INT0 service program>
<5> RETI
Status 1
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(4) Execution of held interrupts (interrupt requests when interrupts are disabled)
RETI
<2> EI
RETI
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(5) Execution of held interrupts two interrupts with lower priority occur concurrently
<INTT0 service routine>
RETI
<1>
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<1> INTCSI
<5>
<3> INTT0
Status 1
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Figure 6-10. Block Diagram of the INT2 and KR0 to KR7 Circuits
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CHAPTER 7 STANDBY FUNCTION
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=
..
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CHAPTER 8 RESET FUNCTION
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Table 8-1. Status of the Hardware after a Reset (1/2)
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CHAPTER 8 RESET FUNCTION Table 8-1. Statuses of the Hardware after a Reset (2/2)
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CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM)
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CHAPTER 10 MASK OPTION
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CHAPTER 11 INSTRUCTION SET
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(3) Explanation of symbols used for the addressing area column
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Note The shaded portion is supported in Mk II mode only.
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APPENDIX A FUNCTIONS OF THE PD75008, PD750008, AND PD75P0016
A
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APPENDIX B DEVELOPMENT TOOLS
*
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PROM programming tools
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APPENDIX B DEVELOPMENT TOOLS
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APPENDIX B DEVELOPMENT TOOLS
+
Development Tool Configuration
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APPENDIX C MASKED ROM ORDERING PROCEDURE
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APPENDIX D INSTRUCTION INDEX
D
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APPENDIX E HARDWARE INDEX
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APPENDIX F REVISION HISTORY
Major revisions in this edition are shown below. The revised chapters refer to this edition.
F
7CHAPTER 1 GENERAL(2) 44-pin plastic QFP (10 x 10 mm)µPD750004GB-XXX-3BS-MTXµPD750006GB-XXX-3BS-MTXµPD750008GB-XXX-3BS-MTXµPD75P0016GB-3BS-MTXNote Connect IC (VPP) to VDD, keeping the wiring as short as possible.Remark ( ) : µPD75P0016.