43
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP
Figure 3-7. µPD750008 I/O Map (4/5)Note Whether a bit can be read or written depends on the bit.
FD0H
FDCH
FDEH
Address
b3 b2 b1 b0
Hardware name (symbol)
R/W
1 bit 4 bits 8 bits
Remarks
Number of bits that can be 
manipulated Bit 
manipulation 
addressing
R/W –
Pull-up resistor specification register group A 
(POGA) R/W –
Pull-up resistor specification register group B 
(POGB)
– –R/W
Clock output mode register (CLOM)
FE2H
Whether this 
location is read- 
or write-
accessible de-
pends on the bit.
FE0H
FE4H
Note
FE6H
FE8H
FECH
R/W
PM33
Port mode register group A (PMGA)
PM63
PM32
PM62
PM31
PM61
PM30
PM60
R/W
Port mode register group B (PMGB)
PM7
PM2
PM5
PM4
FEEH
R/W
Port mode register group C (PMGC)
PM8
CMDD
SBI control register (SBIC)
BSYE
RELD
ACKD
CMDT
ACKE
RELT
ACKT
R/W
CSIE COI WUP
R/W
R/W Serial I/O shift register (SIO)
R/W –
Slave address register (SVA)
Serial operation mode register (CSIM)
(R) (W)
�� – mem.bit
mem.bit